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EDE5116ABSA-5A-E PDF预览

EDE5116ABSA-5A-E

更新时间: 2024-11-08 19:00:47
品牌 Logo 应用领域
尔必达 - ELPIDA 时钟动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
56页 405K
描述
DDR DRAM, 32MX16, 0.5ns, CMOS, PBGA84, MICRO, FBGA-84

EDE5116ABSA-5A-E 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:BGA, BGA84,9X15,32
针数:84Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.82Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:0.5 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):267 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B84内存密度:536870912 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:84字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA84,9X15,32封装形状:RECTANGULAR
封装形式:GRID ARRAY峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8 V认证状态:Not Qualified
刷新周期:8192自我刷新:YES
连续突发长度:4,8子类别:DRAMs
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
Base Number Matches:1

EDE5116ABSA-5A-E 数据手册

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PRELIMINARY DATA SHEET  
512M bits DDR-II SDRAM  
EDE5104ABSA (128M words × 4 bits)  
EDE5108ABSA (64M words × 8 bits)  
EDE5116ABSA (32M words × 16 bits)  
Features  
Description  
The EDE5104AB is a 512M bits DDR-II SDRAM  
1.8V power supply  
organized as 33,554,432 words × 4 bits × 4 banks.  
Double-data-rate architecture: two data transfers per  
clock cycle  
The EDE5108AB is a 512M bits DDR-II SDRAM  
organized as 16,777,216 words × 8 bits × 4 banks.  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
It packaged in 64-ball FBGA (µBGA ) package.  
The EDE5116AB is a 512M bits DDR-II SDRAM  
organized as 8,388,608 words × 16 bits × 4 banks.  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
It is packaged in 84-ball FBGA (µBGA) package.  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
Four internal banks for concurrent operation  
Data mask (DM) for write data  
Burst lengths: 4, 8  
/CAS Latency (CL): 3, 4, 5  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
7.8µs average periodic refresh interval  
1.8V (SSTL_18 compatible) I/O  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation.  
FBGA(µBGA) package is lead free solder (Sn-Ag-Cu)  
Document No. E0323E11 (Ver. 1.1)  
Date Published November 2002 (K) Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2002  

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