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EDE5116AJBG-6ELI-E PDF预览

EDE5116AJBG-6ELI-E

更新时间: 2024-11-23 06:55:55
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
76页 726K
描述
512M bits DDR2 SDRAM WTR (Wide Temperature Range)

EDE5116AJBG-6ELI-E 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA,针数:84
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.33
访问模式:FOUR BANK PAGE BURST最长访问时间:0.45 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B84
JESD-609代码:e1长度:12.5 mm
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:84
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS组织:32MX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.2 mm
自我刷新:YES最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:10 mmBase Number Matches:1

EDE5116AJBG-6ELI-E 数据手册

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PRELIMINARY DATA SHEET  
512M bits DDR2 SDRAM  
WTR (Wide Temperature Range)  
EDE5116AJBG-LI (32M words × 16 bits)  
Specifications  
Features  
Density: 512M bits  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
8M words × 16 bits × 4 banks  
Package  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
84-ball FBGA  
Lead-free (RoHS compliant)  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
Data rate: 667Mbps (max.)  
2KB page size  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Row address: A0 to A12  
Column address: A0 to A9  
Four internal banks for concurrent operation  
Interface: SSTL_18  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Burst lengths (BL): 4, 8  
Burst type (BT):  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Sequential (4, 8)  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
/DQS can be disabled for single-ended Data Strobe  
operation  
Precharge: auto precharge option for each burst  
access  
Wide temperature range  
TC = 40°C to +95°C  
Driver strength: normal/weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period: 7.8µs  
Operating case temperature range  
TC = -40°C to +95°C  
Document No. E1172E20 (Ver. 2.0)  
Date Published September 2007 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2007  

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