Datasheet > EDE5132BABG

EDE5132BABG

更新时间： 2024-09-19 11:45:07

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
74页	721K
描述
512M bits DDR2 SDRAM

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EDE5132BABG 数据手册

PRELIMINARY DATA SHEET

512M bits DDR2 SDRAM

EDE5132BABG (16M words × 32 bits)

Specifications

Features

• Density: 512M bits

• Double-data-rate architecture; two data transfers per

clock cycle

• Organization

• The high-speed data transfer is realized by the 4 bits

prefetch pipelined architecture

4M words × 32 bits × 4 banks

• Package

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

128-ball FBGA

Lead-free (RoHS compliant) and Halogen-free

• Power supply: VDD, VDDQ = 1.5V ± 0.075V

• Data rate: 667Mbps (max.)

• 2KB page size

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

Row address: A0 to A12

Column address: A0 to A8

• Four internal banks for concurrent operation

• Interface: SSTL_18

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Burst lengths (BL): 4, 8

• Burst type (BT):

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

Sequential (4, 8)

• /DQS can be disabled for single-ended Data Strobe

operation

Interleave (4, 8)

• /CAS Latency (CL): 3, 4, 5, 6

• Precharge: auto precharge option for each burst

access

• Driver strength: normal, weak, 1/4

• Refresh: auto-refresh, self-refresh

• Refresh cycles: 8192 cycles/64ms

Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

TC = 0°C to +95°C

Document No. E1372E10 (Ver. 1.0)

Date Published August 2008 (K) Japan

This product became EOL in March, 2010.

Printed in Japan

URL: http://www.elpida.com

Elpida Memory, Inc. 2008

12 3 4 5 6 7...74

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