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EDE5116AHBG-4A-E PDF预览

EDE5116AHBG-4A-E

更新时间: 2024-11-23 12:50:23
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
75页 788K
描述
512M bits DDR2 SDRAM

EDE5116AHBG-4A-E 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA84,9X15,32
针数:84Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.34访问模式:FOUR BANK PAGE BURST
最长访问时间:0.6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):200 MHzI/O 类型:COMMON
交错的突发长度:4,8JESD-30 代码:R-PBGA-B84
长度:12.5 mm内存密度:536870912 bit
内存集成电路类型:DDR DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:84字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:
组织:32MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA84,9X15,32封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.8 V认证状态:Not Qualified
刷新周期:8192座面最大高度:1.2 mm
自我刷新:YES连续突发长度:4,8
最大待机电流:0.008 A子类别:DRAMs
最大压摆率:0.22 mA最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:10 mm
Base Number Matches:1

EDE5116AHBG-4A-E 数据手册

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PRELIMINARY DATA SHEET  
512M bits DDR2 SDRAM  
EDE5108AHBG (64M words × 8 bits)  
EDE5116AHBG (32M words × 16 bits)  
Features  
Specifications  
Density: 512M bits  
Double-data-rate architecture; two data transfers per  
clock cycle  
Organization  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
16M words × 8 bits × 4 banks (EDE5108AHBG)  
8M words × 16 bits × 4 banks (EDE5116AHBG)  
Package  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
60-ball FBGA (EDE5108AHBG)  
84-ball FBGA (EDE5116AHBG)  
Lead-free (RoHS compliant)  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
Data rate: 800Mbps/667Mbps/533Mbps/400Mbps  
transitions  
(max.)  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
1KB page size (EDE5108AHBG)  
Row address: A0 to A13  
Column address: A0 to A9  
2KB page size (EDE5116AHBG)  
Row address: A0 to A12  
Column address: A0 to A9  
Four internal banks for concurrent operation  
Interface: SSTL_18  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
Burst lengths (BL): 4, 8  
Burst type (BT):  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation  
Sequential (4, 8)  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal/weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E0933E30 (Ver. 3.0)  
Date Published September 2006 (K) Japan  
This product became EOL in June, 2010.  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2006  

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