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EDE5116AHSE-8G-E PDF预览

EDE5116AHSE-8G-E

更新时间: 2024-11-26 11:45:07
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器双倍数据速率时钟
页数 文件大小 规格书
81页 871K
描述
512M bits DDR2 SDRAM

EDE5116AHSE-8G-E 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA84,9X15,32
针数:84Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.32.00.28
风险等级:5.34Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:0.4 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):400 MHz
I/O 类型:COMMON交错的突发长度:4,8
JESD-30 代码:R-PBGA-B84长度:12.5 mm
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:84
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:32MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA84,9X15,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:1.8 V
认证状态:Not Qualified刷新周期:8192
座面最大高度:1.2 mm自我刷新:YES
连续突发长度:4,8最大待机电流:0.01 A
子类别:DRAMs最大压摆率:0.195 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmBase Number Matches:1

EDE5116AHSE-8G-E 数据手册

 浏览型号EDE5116AHSE-8G-E的Datasheet PDF文件第2页浏览型号EDE5116AHSE-8G-E的Datasheet PDF文件第3页浏览型号EDE5116AHSE-8G-E的Datasheet PDF文件第4页浏览型号EDE5116AHSE-8G-E的Datasheet PDF文件第5页浏览型号EDE5116AHSE-8G-E的Datasheet PDF文件第6页浏览型号EDE5116AHSE-8G-E的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
512M bits DDR2 SDRAM  
EDE5108AHSE (64M words × 8 bits)  
EDE5116AHSE (32M words × 16 bits)  
Features  
Specifations  
Density: 512M 
Oanizati
Double-data-rate architecture; two data transfers per  
clock cycle  
The high-speed data transfer is realized by the 4 bits  
prefetch pipelined architecture  
16M wnks (EDE5108AHSE)  
8M wonks (EDE5116AHSE)  
Package  
60-ball FBG5108A)  
84-ball FBGA (EDE511SE)  
Lead-free (RoHS coant)  
Power supply: VDD, VDQ = 1.8V 0.1V  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Data rate: 800Mbps/667Mb/533Mbps/400Mbps  
(max.)  
Commands entered on each positive CK edge; data  
1KB page size (EDE5108AHSE)  
Row address: A0 to A13  
Column address: A0 to A9  
2KB page size (EDE5116AHSE)  
Row address: A0 to A12  
Column address: A0 to A9  
Four internal banks for concurrent operation  
Interface: SSTL_18  
and data mask referenced to both edges of DQS  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
O-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Pable RDQS, /RDQS output for making × 8  
compatible to × 4 organization  
S) can be disabled for single-ended  
e operation  
Burst lengths (BL): 4, 8  
Burst type (BT):  
Sequential (4, 8)  
Interleave (4, 8)  
/CAS Latency (CL): 3, 4, 5, 6  
Precharge: auto precharge option for each burst  
access  
Driver strength: normal/weak  
Refresh: auto-refresh, self-refresh  
Refresh cycles: 8192 cycles/64ms  
Average refresh period  
7.8μs at 0°C TC ≤ +85°C  
3.9μs at +85°C < TC ≤ +95°C  
Operating case temperature range  
TC = 0°C to +95°C  
Document No. E0908E40 (Ver. 4.0)  
Date Published December 2006 (K) Japan  
This product became EOL in June, 2010.  
Printed in Japan  
URL: http://www.elpida.com  
©Elpida Memory, Inc. 2006  

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