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CY7C1218H-133AXI PDF预览

CY7C1218H-133AXI

更新时间: 2024-09-17 04:35:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
16页 384K
描述
1-Mbit (32K x36) Pipelined Sync SRAM

CY7C1218H-133AXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP, QFP100,.63X.87针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:4 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:1179648 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:32KX36输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.04 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.225 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:20宽度:14 mm
Base Number Matches:1

CY7C1218H-133AXI 数据手册

 浏览型号CY7C1218H-133AXI的Datasheet PDF文件第2页浏览型号CY7C1218H-133AXI的Datasheet PDF文件第3页浏览型号CY7C1218H-133AXI的Datasheet PDF文件第4页浏览型号CY7C1218H-133AXI的Datasheet PDF文件第5页浏览型号CY7C1218H-133AXI的Datasheet PDF文件第6页浏览型号CY7C1218H-133AXI的Datasheet PDF文件第7页 
CY7C1218H  
1-Mbit (32K x36) Pipelined Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• 32K × 36 common I/O architecture  
The CY7C1218H SRAM integrates 32K x 36 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW[A:D], and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
• 3.3V core power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 3.5 ns (for 166-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium interleaved or linear burst sequences  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous output enable  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
controlled by the Byte Write control inputs. GW when active  
LOW causes all bytes to be written.  
• Available in JEDEC-standard lead-free 100-Pin TQFP  
package  
• “ZZ” Sleep Mode Option  
The CY7C1218H operates from a +3.3V core power supply  
while all outputs may operate either with a +2.5V or +3.3V  
supply. All inputs and outputs are JEDEC-standard  
JESD8-5-compatible.  
Logic Block Diagram  
A0, A1, A  
ADDRESS  
REGISTER  
2
A[1:0]  
MODE  
Q1  
ADV  
CLK  
BURST  
COUNTER  
AND  
CLR  
Q0  
LOGIC  
ADSC  
ADSP  
DQD,DQ  
BYTE  
WRITE REGISTER  
D
DQ  
BYTE  
WRITE DRIVER  
D ,DQPD  
BW  
D
DQ  
BYTE  
WRITE DRIVER  
C ,DQPC  
DQ  
BYTE  
WRITE REGISTER  
C,DQPC  
DQs  
DQP  
DQP  
BW  
C
OUTPUT  
BUFFERS  
A
OUTPUT  
REGISTERS  
MEMORY  
ARRAY  
SENSE  
AMPS  
B
C
DQB,DQP  
B
E
DQB,DQP  
B
DQP  
BYTE  
WRITE DRIVER  
BYTE  
WRITE REGISTER  
BW  
BW  
B
A
DQP  
D
DQA,DQP  
A
DQ  
A ,DQPA  
BYTE  
WRITE DRIVER  
BYTE  
WRITE REGISTER  
BWE  
INPUT  
REGISTERS  
GW  
ENABLE  
REGISTER  
PIPELINED  
ENABLE  
CE  
CE  
CE  
1
2
3
OE  
SLEEP  
CONTROL  
ZZ  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05667 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised July 6, 2006  
[+] Feedback  

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