Datasheet > CY7C1223F

CY7C1223F

更新时间： 2024-11-06 22:40:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
15页	329K
描述
2-Mb (128K x 18) Pipelined DCD Sync SRAM

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CY7C1223F 数据手册

CY7C1223F

2-Mb(128Kx18)PipelinedDCDSyncSRAM

Features

Functional Description^[1]

• Registered inputs and outputs for pipelined operation

• Optimal for performance (Double-Cycle deselect)

— Depth expansion without wait state

The CY7C1223F SRAM integrates 131,072 x 18 SRAM cells

with advanced synchronous peripheral circuitry and a two-bit

counter for internal burst operation. All synchronous inputs are

gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all

addresses, all data inputs, address-pipelining Chip Enable

(CE₁), depth-expansion Chip Enables (CE₂and CE₃), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW_[A:B]and BWE), and Global Write (GW). Asynchronous

inputs include the Output Enable (OE) and the ZZ pin.

Addresses and chip enables are registered at rising edge of

clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent

burst addresses can be internally generated as controlled by

the Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed Write cycle.This part supports Byte Write

operations (see Pin Descriptions and Truth Table for further

details). Write cycles can be one to two bytes wide as

controlled by the byte write control inputs. GW active LOW

causes all bytes to be written. This device incorporates an

additional pipelined enable register which delays turning off

the output buffers an additional cycle when a deselect is

executed.This feature allows depth expansion without penal-

izing system performance.

• 128K × 18-bit common I/O architecture

• 3.3V –5% and +10% core power supply (V_DD

)

• 3.3V I/O supply (V_DDQ

)

• Fast clock-to-output time

— 3.5 ns (for 166-MHz device)

— 4.0 ns (for 133-MHz device)

• Provide high-performance 3-1-1-1 access rate

• User-selectable burst counter supporting Intel^

Pentium^interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100-pin TQFP package and pinout

• “ZZ” Sleep Mode option

The CY7C1223F operates from a +3.3V core power supply

while all outputs operate with a +3.3V supply. All inputs and

outputs are JEDEC-standard JESD8-5-compatible.

Selection Guide

166 MHz 133 MHz

Unit

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

3.5

240

4.0

225

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of this part.

Note:

1. . For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05418 Rev. *A

Revised April 10, 2004

12 3 4 5 6 7...15

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与CY7C1223F相关器件

型号	品牌	获取价格	描述	数据表
CY7C1223F-133AC	CYPRESS	获取价格	2-Mb (128K x 18) Pipelined DCD Sync SRAM
CY7C1223F-133ACT	CYPRESS	获取价格	Standard SRAM, 128KX18, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CY7C1223H	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined DCD Sync SRAM
CY7C1223H-133AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined DCD Sync SRAM
CY7C1223H-133AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined DCD Sync SRAM
CY7C1223H-166AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined DCD Sync SRAM
CY7C1223H-166AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Pipelined DCD Sync SRAM
CY7C123-10DMB	ETC	获取价格	x4 SRAM
CY7C123-10KMB	CYPRESS	获取价格	Standard SRAM, 256X4, 10ns, CMOS, CDFP24, CERPACK-24
CY7C123-10LMB	ETC	获取价格	x4 SRAM

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