CY7C1219F
1-Mbit (32K x 36) Pipelined DCD Sync
SRAM
Features
Functional Description[1]
• Registered inputs and outputs for pipelined operation
• Optimal for performance (Double-Cycle deselect)
— Depth expansion without wait state
The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a two-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
Clock Input (CLK). The synchronous inputs include all
addresses, all data inputs, address-pipelining Chip Enable
Control inputs (ADSC, ADSP, and ADV2), Write Enables
(BW[A:D], and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent
burst addresses can be internally generated as controlled by
the Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports Byte Write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to four bytes wide as
controlled by the byte write control inputs. GW active LOW
causes all bytes to be written. This device incorporates an
additional pipelined enable register which delays turning off
the output buffers an additional cycle when a deselect is
executed.This feature allows depth expansion without penal-
izing system performance.
• 32K × 36-bit common I/O architecture
• 3.3V –5% and +10% core power supply (VDD
)
(
), depth-expansion Chip Enables (CE and
), Burst
CE3
CE1
• 3.3V I/O supply (VDDQ
)
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 4.0 ns (for 133-MHz device)
• Provide high-performance 3-1-1-1 access rate
• User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
• Separate processor and controller address strobes
• Synchronous self-timed writes
• Asynchronous Output Enable
• JEDEC-standard 100-pin TQFP package and pinout
• “ZZ” Sleep Mode option
The CY7C1219F operates from a +3.3V core power supply
while all outputs operate with a +3.3V supply. All inputs and
outputs are JEDEC-standard JESD8-5-compatible.
Selection Guide
166 MHz
3.5
133 MHz
4.0
Unit
ns
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
240
40
225
40
mA
mA
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05416 Rev. *A
Revised April 10, 2004