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CY7C1223F-133AC PDF预览

CY7C1223F-133AC

更新时间： 2024-11-06 22:44:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
15页 329K
描述
2-Mb (128K x 18) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1223F-133AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP,
针数：100Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.85最长访问时间：4 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：2359296 bit内存集成电路类型：STANDARD SRAM
内存宽度：18湿度敏感等级：3
功能数量：1端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.63 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD (800)端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

CY7C1223F-133AC 数据手册

 浏览型号CY7C1223F-133AC的Datasheet PDF文件第2页浏览型号CY7C1223F-133AC的Datasheet PDF文件第3页浏览型号CY7C1223F-133AC的Datasheet PDF文件第4页浏览型号CY7C1223F-133AC的Datasheet PDF文件第5页浏览型号CY7C1223F-133AC的Datasheet PDF文件第6页浏览型号CY7C1223F-133AC的Datasheet PDF文件第7页 
CY7C1223F  
2-Mb(128Kx18)PipelinedDCDSyncSRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
— Depth expansion without wait state  
The CY7C1223F SRAM integrates 131,072 x 18 SRAM cells  
with advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW[A:B] and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two bytes wide as  
controlled by the byte write control inputs. GW active LOW  
causes all bytes to be written. This device incorporates an  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• 128K × 18-bit common I/O architecture  
• 3.3V –5% and +10% core power supply (VDD  
)
• 3.3V I/O supply (VDDQ  
)
• Fast clock-to-output time  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• JEDEC-standard 100-pin TQFP package and pinout  
• “ZZ” Sleep Mode option  
The CY7C1223F operates from a +3.3V core power supply  
while all outputs operate with a +3.3V supply. All inputs and  
outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
166 MHz 133 MHz  
Unit  
ns  
mA  
mA  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
3.5  
240  
40  
4.0  
225  
40  
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of this part.  
Note:  
1. . For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05418 Rev. *A  
Revised April 10, 2004  
1234567...15

中文翻译

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CY7C1223F-133AC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1223H-166AXC CYPRESS

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