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CY7C1223H-133AXC PDF预览

CY7C1223H-133AXC

更新时间: 2024-11-07 02:55:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
16页 706K
描述
2-Mbit (128K x 18) Pipelined DCD Sync SRAM

CY7C1223H-133AXC 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:QFP包装说明:LQFP, QFP100,.63X.87
针数:100Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.8Is Samacsys:N
最长访问时间:4 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):133 MHzI/O 类型:COMMON
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:2359296 bit
内存集成电路类型:CACHE SRAM内存宽度:18
湿度敏感等级:3功能数量:1
端子数量:100字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装等效代码:QFP100,.63X.87封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5/3.3,3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.04 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.225 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

CY7C1223H-133AXC 数据手册

 浏览型号CY7C1223H-133AXC的Datasheet PDF文件第2页浏览型号CY7C1223H-133AXC的Datasheet PDF文件第3页浏览型号CY7C1223H-133AXC的Datasheet PDF文件第4页浏览型号CY7C1223H-133AXC的Datasheet PDF文件第5页浏览型号CY7C1223H-133AXC的Datasheet PDF文件第6页浏览型号CY7C1223H-133AXC的Datasheet PDF文件第7页 
CY7C1223H  
2-Mbit (128K x 18) Pipelined DCD Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
— Depth expansion without wait state  
• 128K × 18-bit common I/O architecture  
• 3.3V core power supply  
The CY7C1223H SRAM integrates 128K x 18 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW[A:B] and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
• 3.3V/2.5V I/O supply  
• Fast clock-to-output time  
— 3.5 ns (for 166-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
— 4.0 ns (for 133-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to two bytes wide as  
controlled by the byte write control inputs. GW active LOW  
causes all bytes to be written. This device incorporates an  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
• Asynchronous Output Enable  
• Offered in JEDEC-standard lead-free 100-pin TQFP  
package  
• “ZZ” Sleep Mode option  
The CY7C1223H operates from a +3.3V core power supply  
while all outputs operate with either a +3.3V/2.5V supply. All  
inputs and outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
240  
225  
mA  
mA  
Maximum CMOS Standby Current  
40  
40  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05674 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 6, 2006  
[+] Feedback  

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