CY7C1231H-133AXI

更新时间： 2024-11-09 02:58:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	533K
描述
2-Mbit (128K x 18) Flow-Through SRAM with NoBL⑩ Architecture

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY7C1231H-133AXI 数据手册

CY7C1231H

2-Mbit (128K x 18) Flow-Through SRAM

with NoBL™ Architecture

Functional Description^[1]

Features

• Can support up to 133-MHz bus operations with zero

wait states

The CY7C1231H is a 3.3V/2.5V, 128K x 18 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1231H is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 6.5 ns (133-MHz

device).

• 128K x 18 common I/O architecture

• 3.3V core power supply

• 3.3V/2.5V I/O operation

• Fast clock-to-output times

Write operations are controlled by the two Byte Write Select

(BW_[A:B]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

— 6.5 ns (133-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed write

• Asynchronous Output Enable

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. In order to avoid bus

contention, the output drivers are synchronously tri-stated

during the data portion of a write sequence.

• Offered in JEDEC-standard lead-free 100-pin TQFP

package

• Burst Capability—linear or interleaved burst order

• Low standby power

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

MODE

BURST

LOGIC

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

MEMORY

ARRAY

WRITE

DRIVERS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

DQs

DQP

INPUT

READ LOGIC

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-00207 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 26, 2006

[+] Feedback

12 3 4 5 6 7...12

中文翻译

下载PDF

与CY7C1231H-133AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C123-7DC	CYPRESS	获取价格	Standard SRAM, 256X4, 7ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
CY7C123-7LC	ETC	获取价格	x4 SRAM
CY7C123-7VCR	CYPRESS	获取价格	Standard SRAM, 256X4, 7ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24
CY7C123-7VCT	CYPRESS	获取价格	Standard SRAM, 256X4, 7ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24
CY7C123-9DC	ETC	获取价格	x4 SRAM
CY7C123-9LC	ETC	获取价格	x4 SRAM
CY7C123-9VCR	CYPRESS	获取价格	Standard SRAM, 256X4, 9ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24
CY7C123-9VCT	CYPRESS	获取价格	Standard SRAM, 256X4, 9ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24
CY7C12411KV18	CYPRESS	获取价格	36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1241KV18	CYPRESS	获取价格	36-Mbit QDRÂ® II SRAM 4-Word Burst Architectu

与CY7C1231H-133AXI相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

22
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

21
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

48
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

39

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1231H-133AXI

CY7C1231H-133AXI 数据手册

与CY7C1231H-133AXI相关器件

与CY7C1231H-133AXI相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1231H-133AXI

CY7C1231H-133AXI 数据手册

与CY7C1231H-133AXI相关器件

与CY7C1231H-133AXI相关文章

您还可以找

您在本页遇到什么问题？