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CY7C1243KV18-400BZC PDF预览

CY7C1243KV18-400BZC

更新时间: 2024-11-26 12:43:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
28页 913K
描述
36-Mbit QDR® II SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

CY7C1243KV18-400BZC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:13 X 15 MM, 1.40 MM HEIGHT, MO-216, FBGA-165
针数:165Reach Compliance Code:not_compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.65最长访问时间:0.45 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):400 MHz
I/O 类型:SEPARATEJESD-30 代码:R-PBGA-B165
长度:15 mm内存密度:37748736 bit
内存集成电路类型:QDR SRAM内存宽度:18
功能数量:1端子数量:165
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:2MX18
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL电源:1.5/1.8,1.8 V
认证状态:Not Qualified座面最大高度:1.4 mm
最大待机电流:0.31 A最小待机电流:1.7 V
子类别:SRAMs最大压摆率:0.66 mA
最大供电电压 (Vsup):1.9 V最小供电电压 (Vsup):1.7 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:13 mm
Base Number Matches:1

CY7C1243KV18-400BZC 数据手册

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CY7C1241KV18, CY7C1256KV18  
CY7C1243KV18, CY7C1245KV18  
36-Mbit QDR® II+ SRAM 4-Word Burst  
Architecture (2.0 Cycle Read Latency)  
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)  
Features  
Configurations  
Separate independent read and write data ports  
Supports concurrent transactions  
With Read Cycle Latency of 2.0 cycles:  
CY7C1241KV18 – 4 M × 8  
450 MHz clock for high bandwidth  
CY7C1256KV18 – 4 M × 9  
CY7C1243KV18 – 2 M × 18  
CY7C1245KV18 – 1 M × 36  
4-word burst for reducing address bus frequency  
Double data rate (DDR) interfaces on both read and write ports  
(data transferred at 900 MHz) at 450 MHz  
Functional Description  
Available in 2.0 clock cycle latency  
The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and  
CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs,  
equipped with QDR II+ architecture. Similar to QDR II  
architecture, QDR II+ architecture consists of two separate ports:  
the read port and the write port to access the memory array. The  
read port has dedicated data outputs to support read operations  
and the write port has dedicated data inputs to support write  
operations. QDR II+ architecture has separate data inputs and  
data outputs to completely eliminate the need to “turnaround” the  
data bus that exists with common I/O devices. Each port is  
accessed through a common address bus. Addresses for read  
and write addresses are latched on alternate rising edges of the  
input (K) clock. Accesses to the QDR II+ read and write ports are  
completely independent of one another. To maximize data  
throughput, both read and write ports are equipped with DDR  
interfaces. Each address location is associated with four 8-bit  
words (CY7C1241KV18), 9-bit words (CY7C1256KV18), 18-bit  
words (CY7C1243KV18), or 36-bit words (CY7C1245KV18) that  
burst sequentially into or out of the device. Because data is  
transferred into and out of the device on every rising edge of both  
input clocks (K and K), memory bandwidth is maximized while  
simplifying system design by eliminating bus “turnarounds”.  
Two input clocks (K and K) for precise DDR timing  
SRAM uses rising edges only  
Echo clocks (CQ and CQ) simplify data capture in high speed  
systems  
Data valid pin (QVLD) to indicate valid data on the output  
Single multiplexed address input bus latches address inputs  
for read and write ports  
Separate port selects for depth expansion  
Synchronous internally self-timed writes  
QDR® II+ operates with 2.0 cycle read latency when DOFF is  
asserted HIGH  
OperatessimilartoQDRIdevicewith1cyclereadlatencywhen  
DOFF is asserted LOW  
Available in × 8, × 9, × 18, and × 36 configurations  
Full data coherency, providing most current data  
[1]  
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD  
Supports both 1.5 V and 1.8 V I/O supply  
HSTL inputs and variable drive HSTL output buffers  
Available in 165-ball FBGA package (13 × 15 × 1.4 mm)  
Offered in both Pb-free and non Pb-free packages  
JTAG 1149.1 compatible test access port  
Depth expansion is accomplished with port selects, which  
enables each port to operate independently.  
All synchronous inputs pass through input registers controlled by  
the K or K input clocks. All data outputs pass through output  
registers controlled by the K or K input clocks. Writes are  
conducted with on-chip synchronous self-timed write circuitry.  
Phase-locked loop (PLL) for accurate data placement  
Table 1. Selection Guide  
Description  
Maximum operating frequency  
450 MHz  
400 MHz  
400  
375 MHz  
375  
333 MHz  
333  
Unit  
MHz  
mA  
450  
710  
710  
720  
1020  
Maximum operating current  
× 8  
× 9  
650  
620  
560  
650  
620  
560  
× 18  
× 36  
660  
630  
570  
920  
870  
790  
Note  
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V  
= 1.4 V to V  
.
DD  
DDQ  
Cypress Semiconductor Corporation  
Document Number: 001-57832 Rev. *B  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 24, 2011  
[+] Feedback  

CY7C1243KV18-400BZC 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1263KV18-400BZC CYPRESS

完全替代

36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
CY7C1263KV18-400BZI CYPRESS

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36-Mbit QDR? II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)

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