CY7C12411KV18, CY7C12561KV18
CY7C12431KV18, CY7C12451KV18
36-Mbit QDR® II+ SRAM 4-Word Burst
Architecture (2.0 Cycle Read Latency)
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
Features
Functional Description
■ Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
The CY7C12411KV18, CY7C12561KV18, CY7C12431KV18,
and CY7C12451KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II
architecture, QDR II+ architecture consists of two separate ports:
the read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to eliminate the need to “turnaround” the data bus
that exists with common I/O devices. Each port is accessed
through a common address bus. Addresses for read and write
addresses are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C12411KV18), 9-bit words (CY7C12561KV18),
■ 450 MHz Clock for High Bandwidth
■ 4-word Burst for Reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces on both Read and Write
Ports (Data transferred at 900 MHz) at 450 MHz
■ Available in 2.0 Clock Cycle Latency
■ Two Input Clocks (K and K) for Precise DDR Timing
❐ SRAM uses rising edges only
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Data Valid Pin (QVLD) to indicate Valid Data on the Output
■ Single Multiplexed Address Input Bus Latches Address Inputs
for Read and Write Ports
18-bit
words
(CY7C12431KV18),
or
36-bit
words
(CY7C12451KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of both input clocks (K and K), memory
bandwidth is maximized while simplifying system design by
eliminating bus “turnarounds”.
■ Separate Port Selects for Depth Expansion
■ Synchronous Internally Self Timed Writes
■ QDR® II+ operates with 2.0 Cycle Read Latency when DOFF
is asserted HIGH
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■ Operates similar to QDR-I Device with 1 Cycle Read Latency
when DOFF is asserted LOW
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ Available in x8, x9, x18, and x36 Configurations
■ Full Data Coherency, providing most Current Data
These devices are down bonded from the 65nm 72M
QDRII+/DDRII+ devices and hence have the same IDD/ISB1
values and the same JTAG ID code as the equivalent 72M device
options. For details refer to the application note AN53189, 65nm
Technology InterimQDRII+/DDRII+ SRAM device family
description.
[1]
■ Core VDD = 1.8V± 0.1V; I/O VDDQ = 1.4V to VDD
❐ Supports both 1.5V and 1.8V I/O supply
■ HSTL Inputs and Variable Drive HSTL Output Buffers
■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
Table 1. Selection Guide
450 400 375 333
■ JTAG 1149.1 Compatible Test Access Port
Description
Unit
■ Phase Locked Loop (PLL) for Accurate Data Placement
MHz MHz MHz MHz
Max Operating Frequency
Max Operating Current
450 400 375 333 MHz
x8 760 690 660 600 mA
x9 760 690 660 600
Configurations
With Read Cycle Latency of 2.0 cycles:
CY7C12411KV18 – 4M x 8
x18 780 710 680 620
x36 1100 1000 950 850
CY7C12561KV18 – 4M x 9
CY7C12431KV18 – 2M x 18
CY7C12451KV18 – 1M x 36
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4V to V
.
DD
DDQ
Cypress Semiconductor Corporation
Document Number: 001-53192 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 31, 2011
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