Datasheet > CY7C1231F_05

CY7C1231F_05

更新时间： 2024-09-17 05:09:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	209K
描述
2-Mbit (128K x 18) Flow-through SRAM with NoBL⑩ Architecture

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CY7C1231F_05 数据手册

CY7C1231F

2-Mbit (128K x 18) Flow-through SRAM with

NoBL™ Architecture

Features

Functional Description^[1]

• Can support up to 117-MHz bus operations with zero

wait states

The CY7C1231F is a 3.3V, 128K x 18 Synchronous

Flow-through Burst SRAM designed specifically to support

unlimited true back-to-back Read/Write operations without the

insertion of wait states. The CY7C1231F is equipped with the

advanced No Bus Latency™ (NoBL™) logic required to

enable consecutive Read/Write operations with data being

transferred on every clock cycle. This feature dramatically

improves the throughput of data through the SRAM, especially

in systems that require frequent Write-Read transitions.

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™

devices

• Internally self-timed output buffer control to eliminate

the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock cycle.

Maximum access delay from the clock rise is 7.5 ns (117-MHz

device).

• 128K x 18 common I/O architecture

• Single 3.3V power supply

• Fast clock-to-output times

— 7.5 ns (for 117-MHz device)

Write operations are controlled by the two Byte Write Select

(BW_[A:B]) and a Write Enable (WE) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

— 8.5 ns (for 100-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power

Three synchronous Chip Enables (CE₁, CE₂, CE₃) and an

asynchronous Output Enable (OE) provide for easy bank

selection and output three-state control. In order to avoid bus

contention, the output drivers are synchronously three-stated

during the data portion of a write sequence.

Logic Block Diagram

ADDRESS

A0, A1, A

A1'

A0'

MODE

BURST

LOGIC

ADV/LD

CLK

CEN

WRITE ADDRESS

ADV/LD

MEMORY

ARRAY

WRITE

DRIVERS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

DQs

DQP

INPUT

READ LOGIC

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05437 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised May 31, 2005

12 3 4 5 6 7...12

中文翻译

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与CY7C1231F_05相关器件

型号	品牌	获取价格	描述	数据表
CY7C1231F-100	CYPRESS	获取价格	2-Mbit (128K x 18) Flow-through SRAM with NoBL Architecture
CY7C1231F-100AC	CYPRESS	获取价格	2-Mbit (128K x 18) Flow-through SRAM with NoB
CY7C1231F-117	CYPRESS	获取价格	2-Mbit (128K x 18) Flow-through SRAM with NoBL Architecture
CY7C1231H	CYPRESS	获取价格	2-Mbit (128K x 18) Flow-Through SRAM with NoB
CY7C1231H-133AXC	CYPRESS	获取价格	2-Mbit (128K x 18) Flow-Through SRAM with NoB
CY7C1231H-133AXCT	CYPRESS	获取价格	暂无描述
CY7C1231H-133AXI	CYPRESS	获取价格	2-Mbit (128K x 18) Flow-Through SRAM with NoB
CY7C123-7DC	CYPRESS	获取价格	Standard SRAM, 256X4, 7ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
CY7C123-7LC	ETC	获取价格	x4 SRAM
CY7C123-7VCR	CYPRESS	获取价格	Standard SRAM, 256X4, 7ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24

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