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CY7C1219F-133ACT PDF预览

CY7C1219F-133ACT

更新时间： 2024-09-17 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
15页 333K
描述
Cache SRAM, 32KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100

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CY7C1219F-133ACT 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
最长访问时间：4 ns其他特性：PIPELINED ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：1179648 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：100
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：32KX36
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

CY7C1219F-133ACT 数据手册

 浏览型号CY7C1219F-133ACT的Datasheet PDF文件第2页浏览型号CY7C1219F-133ACT的Datasheet PDF文件第3页浏览型号CY7C1219F-133ACT的Datasheet PDF文件第4页浏览型号CY7C1219F-133ACT的Datasheet PDF文件第5页浏览型号CY7C1219F-133ACT的Datasheet PDF文件第6页浏览型号CY7C1219F-133ACT的Datasheet PDF文件第7页 
CY7C1219F  
1-Mbit (32K x 36) Pipelined DCD Sync  
SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
— Depth expansion without wait state  
The CY7C1219F SRAM integrates 32,768 x 36 SRAM cells  
with advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
Control inputs (ADSC, ADSP, and ADV2), Write Enables  
(BW[A:D], and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
controlled by the byte write control inputs. GW active LOW  
causes all bytes to be written. This device incorporates an  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• 32K × 36-bit common I/O architecture  
• 3.3V –5% and +10% core power supply (VDD  
)
(
), depth-expansion Chip Enables (CE and  
), Burst  
CE3  
CE1  
• 3.3V I/O supply (VDDQ  
)
• Fast clock-to-output times  
— 3.5 ns (for 166-MHz device)  
— 4.0 ns (for 133-MHz device)  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel  
Pentiuminterleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed writes  
• Asynchronous Output Enable  
• JEDEC-standard 100-pin TQFP package and pinout  
• “ZZ” Sleep Mode option  
The CY7C1219F operates from a +3.3V core power supply  
while all outputs operate with a +3.3V supply. All inputs and  
outputs are JEDEC-standard JESD8-5-compatible.  
Selection Guide  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
240  
40  
225  
40  
mA  
mA  
Shaded area contains advance information. Please contact your local Cypress sales representative for availability of this part.  
Notes:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05416 Rev. *A  
Revised April 10, 2004  
1234567...15

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CY7C122-15DC CYPRESS

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