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CY7C1219H-100AXI PDF预览

CY7C1219H-100AXI

更新时间： 2024-11-09 03:14:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
16页 360K
描述
1-Mbit (32K x 36) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1219H-100AXI 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP, QFP100,.63X.87针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.8
Is Samacsys：N最长访问时间：3.5 ns
其他特性：PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：166 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：1179648 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：100
字数：32768 words字数代码：32000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：32KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：2.5/3.3,3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.04 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.24 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：20
宽度：14 mmBase Number Matches：1

CY7C1219H-100AXI 数据手册

 浏览型号CY7C1219H-100AXI的Datasheet PDF文件第2页浏览型号CY7C1219H-100AXI的Datasheet PDF文件第3页浏览型号CY7C1219H-100AXI的Datasheet PDF文件第4页浏览型号CY7C1219H-100AXI的Datasheet PDF文件第5页浏览型号CY7C1219H-100AXI的Datasheet PDF文件第6页浏览型号CY7C1219H-100AXI的Datasheet PDF文件第7页 
CY7C1219H  
1-Mbit (32K x 36) Pipelined DCD Sync SRAM  
Features  
Functional Description[1]  
• Registered inputs and outputs for pipelined operation  
• Optimal for performance (Double-Cycle deselect)  
— Depth expansion without wait state  
The CY7C1219H SRAM integrates 32K x 36 SRAM cells with  
advanced synchronous peripheral circuitry and a two-bit  
counter for internal burst operation. All synchronous inputs are  
gated by registers controlled by a positive-edge-triggered  
Clock Input (CLK). The synchronous inputs include all  
addresses, all data inputs, address-pipelining Chip Enable  
(CE1), depth-expansion Chip Enables (CE2 and CE3), Burst  
Control inputs (ADSC, ADSP, and ADV), Write Enables  
(BW[A:D], and BWE), and Global Write (GW). Asynchronous  
inputs include the Output Enable (OE) and the ZZ pin.  
• 32K × 36-bit common I/O architecture  
• 3.3V core power supply (VDD  
)
• 2.5V/3.3V I/O power supply (VDDQ  
)
• Fast clock-to-output times  
— 3.5 ns (for 166-MHz device)  
Addresses and chip enables are registered at rising edge of  
clock when either Address Strobe Processor (ADSP) or  
Address Strobe Controller (ADSC) are active. Subsequent  
burst addresses can be internally generated as controlled by  
the Advance pin (ADV).  
• Provide high-performance 3-1-1-1 access rate  
• User-selectable burst counter supporting Intel®  
Pentium® interleaved or linear burst sequences  
• Separate processor and controller address strobes  
• Synchronous self-timed write  
Address, data inputs, and write controls are registered on-chip  
to initiate a self-timed Write cycle.This part supports Byte Write  
operations (see Pin Descriptions and Truth Table for further  
details). Write cycles can be one to four bytes wide as  
controlled by the byte write control inputs. GW active LOW  
causes all bytes to be written. This device incorporates an  
additional pipelined enable register which delays turning off  
the output buffers an additional cycle when a deselect is  
executed.This feature allows depth expansion without penal-  
izing system performance.  
• Asynchronous Output Enable  
• Available in JEDEC-standard lead-free 100-Pin TQFP  
package  
• “ZZ” Sleep Mode option  
The CY7C1219H operates from a +3.3V core power supply  
while all outputs operate with either a +2.5V or +3.3V supply.  
All  
inputs  
and  
outputs  
are  
JEDEC-standard  
JESD8-5-compatible.  
Selection Guide  
166 MHz  
3.5  
133 MHz  
4.0  
Unit  
ns  
Maximum Access Time  
Maximum Operating Current  
Maximum CMOS Standby Current  
240  
225  
mA  
mA  
40  
40  
Note:  
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05664 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised July 5, 2006  
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