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CY62148V-70SC PDF预览

CY62148V-70SC

更新时间: 2024-02-18 13:29:57
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
7页 213K
描述
Standard SRAM, 512KX8, 70ns, CMOS, PDSO32, 0.450 INCH, PLASTIC, SOIC-32

CY62148V-70SC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:0.450 INCH, PLASTIC, SOIC-32针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.71
最长访问时间:70 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32JESD-609代码:e0
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):225
电源:3 V认证状态:Not Qualified
最大待机电流:0.0005 A最小待机电流:2.7 V
子类别:SRAMs最大压摆率:0.05 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30Base Number Matches:1

CY62148V-70SC 数据手册

 浏览型号CY62148V-70SC的Datasheet PDF文件第2页浏览型号CY62148V-70SC的Datasheet PDF文件第3页浏览型号CY62148V-70SC的Datasheet PDF文件第4页浏览型号CY62148V-70SC的Datasheet PDF文件第5页浏览型号CY62148V-70SC的Datasheet PDF文件第6页浏览型号CY62148V-70SC的Datasheet PDF文件第7页 
fax id: 1093  
PRELIMINARY  
CY62148V  
512K x 8 Static RAM  
an automatic power-down feature that reduces power con-  
sumption by more than 99% when deselected.  
Features  
• 2.7V3.6V operation  
• CMOS for optimum speed/power  
• Low active power  
Writing to the device is accomplished by taking chip enable  
(CE) and write enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O through I/O ) is then written into the location speci-  
0
7
fied on the address pins (A through A ).  
0
18  
— 180 mW (max.)  
Reading from the device is accomplished by taking chip en-  
able (CE) and output enable (OE) LOW while forcing write en-  
able (WE) HIGH for read. Under these conditions, the contents  
of the memory location specified by the address pins will ap-  
pear on the I/O pins.  
• Low standby power (Commercial LL version)  
— 54 µW (max.)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE options  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY62148V is a high-performance CMOS static RAM or-  
ganized as 524,288 words by 8 bits. Easy memory expansion  
is provided by an active LOW chip enable (CE), an active LOW  
output enable (OE), and three-state drivers. This device has  
The CY62148V is available in a standard 32 pin 450-mil-wide  
body width SOIC and 32 pin TSOPII packages.  
Logic Block Diagram  
Pin Configuration  
Top View  
SOIC  
TSOPII  
A
V
CC  
32  
31  
30  
17  
1
A
A
A
16  
A
A
2
3
4
15  
14  
12  
18  
29  
28  
WE  
5
A
A
A
A
A
A
7
13  
27  
26  
6
6
8
I/O  
5
7
0
9
INPUT BUFFER  
25  
24  
23  
22  
21  
A
A
3
8
9
10  
11  
12  
13  
4
A
11  
OE  
I/O  
I/O  
1
2
A
A
CE  
I/O  
I/O  
I/O  
A
0
2
10  
A
1
A
1
4
7
A
0
A
I/O  
0
I/O  
1
I/O  
2
6
5
4
3
20  
19  
A
5
6
14  
15  
16  
A
I/O  
I/O  
I/O  
I/O  
I/O  
18  
17  
3
4
5
A
7
512K x 8  
ARRAY  
GND  
A
A
12  
14  
16  
62148V-2  
A
A17  
I/O  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
62148V-1  
OE  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
December 9, 1997  

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