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CY62157CV25LL-70BAI PDF预览

CY62157CV25LL-70BAI

更新时间： 2024-11-19 22:18:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 280K
描述
512K x 16 Static RAM

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中文翻译

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CY62157CV25LL-70BAI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.75最长访问时间：70 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e0长度：10 mm
内存密度：8388608 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
电源：2.5 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.00002 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.015 mA最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.2 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：6 mm
Base Number Matches：1

CY62157CV25LL-70BAI 数据手册

 浏览型号CY62157CV25LL-70BAI的Datasheet PDF文件第2页浏览型号CY62157CV25LL-70BAI的Datasheet PDF文件第3页浏览型号CY62157CV25LL-70BAI的Datasheet PDF文件第4页浏览型号CY62157CV25LL-70BAI的Datasheet PDF文件第5页浏览型号CY62157CV25LL-70BAI的Datasheet PDF文件第6页浏览型号CY62157CV25LL-70BAI的Datasheet PDF文件第7页 
CY62157CV25/30/33  
MoBL™  
512K x 16 Static RAM  
reducing power consumption by more than 99% when dese-  
lected (CE1 HIGH or CE2 LOW or both BLE and BHE are  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE1 HIGH or  
CE2 LOW), outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),  
or during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW).  
Features  
• High speed  
— 55 ns and 70 ns availability  
• Voltage range:  
— CY62157CV25: 2.2V–2.7V  
— CY62157CV30: 2.7V–3.3V  
— CY62157CV33: 3.0V–3.6V  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from  
I/O pins (I/O0 through I/O7), is written into the location speci-  
fied on the address pins (A0 through A18). If Byte High Enable  
(BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is  
written into the location specified on the address pins (A0  
through A18).  
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)  
• Low standby power  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW and Chip Enable  
2 (CE2) HIGH while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins will appear on I/O0 to  
I/O7. If Byte High Enable (BHE) is LOW, then data from mem-  
ory will appear on I/O8 to I/O15. See the truth table at the back  
of this data sheet for a complete description of read and write  
modes.  
Functional Description  
The CY62157CV25/30/33 are high-performance CMOS static  
RAMs organized as 512K words by 16 bits. These devices  
feature advanced circuit design to provide ultra-low active cur-  
rent. This is ideal for providing More Battery Life™ (MoBL™)  
in portable applications such as cellular telephones. The de-  
vices also have an automatic power-down feature that signifi-  
cantly reduces power consumption by 80% when addresses  
are not toggling. The device can also be put into standby mode  
The CY62157CV25/30/33 are available in a 48-ball FBGA  
package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
10  
9
8
7
6
512K × 16  
5
4
3
2
RAM Array  
2048 × 4096  
I/O –I/O  
0
7
I/O –I/O  
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
2
CE  
1
OE  
BLE  
Power-down  
Circuit  
CE  
2
BHE  
BLE  
CE  
1
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05014 Rev. *C  
Revised April 23, 2002  
1234567...13

中文翻译

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与CY62157CV25LL-70BAI相关器件

型号 品牌 获取价格 描述 数据表
CY62157CV25LL-70BAIT CYPRESS

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 		Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30 CYPRESS

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 		512K x 16 Static RAM
CY62157CV30LL-55BAI CYPRESS

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 		512K x 16 Static RAM
CY62157CV30LL-55BAI ROCHESTER

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 		512KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30LL-70BAE CYPRESS

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 		512K x 16 Static RAM
CY62157CV30LL-70BAET CYPRESS

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 		暂无描述
CY62157CV30LL-70BAI CYPRESS

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 		512K x 16 Static RAM
CY62157CV30LL-70BAI ROCHESTER

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 		512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30LL-70BAIT ROCHESTER

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 		512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30LL-70BAIT CYPRESS

获取价格

 		Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48

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