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CY62157CV33LL-55BAIT PDF预览

CY62157CV33LL-55BAIT

更新时间： 2024-11-24 20:43:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 209K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48

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CY62157CV33LL-55BAIT 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：TFBGA,
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.6最长访问时间：55 ns
JESD-30 代码：R-PBGA-B48JESD-609代码：e0
长度：10 mm内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mmBase Number Matches：1

CY62157CV33LL-55BAIT 数据手册

 浏览型号CY62157CV33LL-55BAIT的Datasheet PDF文件第2页浏览型号CY62157CV33LL-55BAIT的Datasheet PDF文件第3页浏览型号CY62157CV33LL-55BAIT的Datasheet PDF文件第4页浏览型号CY62157CV33LL-55BAIT的Datasheet PDF文件第5页浏览型号CY62157CV33LL-55BAIT的Datasheet PDF文件第6页浏览型号CY62157CV33LL-55BAIT的Datasheet PDF文件第7页 
CY62157CV25/30/33  
512K x 16 Static RAM  
(MoBL™) in portable applications such as cellular telephones.  
The devices also have an automatic power-down feature that  
significantly reduces power consumption by 80% when  
addresses are not toggling. The device can also be put into  
standby mode reducing power consumption by more than 99%  
when deselected (CE1 HIGH or CE2 LOW or both BLE and  
BHE are HIGH). The input/output pins (I/O0 through I/O15) are  
placed in a high-impedance state when: deselected (CE1  
HIGH or CE2 LOW), outputs are disabled (OE HIGH), both  
Byte High Enable and Byte Low Enable are disabled (BHE,  
BLE HIGH), or during a write operation (CE1 LOW and CE2  
HIGH and WE LOW).  
Features  
• Temperature Ranges  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• High speed  
— 55 ns and 70 ns availability  
• Voltage range:  
— CY62157CV25: 2.2V–2.7V  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) and Write Enable (WE) inputs LOW and Chip Enable 2  
(CE2) HIGH. If Byte Low Enable (BLE) is LOW, then data from  
I/O pins (I/O0 through I/O7), is written into the location  
specified on the address pins (A0 through A18). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A18).  
— CY62157CV30: 2.7V–3.3V  
— CY62157CV33: 3.0V–3.6V  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)  
• Low standby power  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) and Output Enable (OE) LOW and Chip  
Enable 2 (CE2) HIGH while forcing the Write Enable (WE)  
HIGH. If Byte Low Enable (BLE) is LOW, then data from the  
memory location specified by the address pins will appear on  
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory will appear on I/O8 to I/O15. See the truth table at the  
back of this data sheet for a complete description of read and  
write modes.  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Functional Description[1]  
The CY62157CV25/30/33 are high-performance CMOS static  
RAMs organized as 512K words by 16 bits. These devices  
feature advanced circuit design to provide ultra-low active  
current. This is ideal for providing More Battery Life™  
The CY62157CV25/30/33 are available in a 48-ball FBGA  
package.  
Logic Block Diagram  
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
10  
9
8
7
6
512K × 16  
5
4
3
2
RAM Array  
2048 × 4096  
I/O –I/O  
0
7
I/O –I/O  
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Power-down  
Circuit  
CE2  
CE1  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05014 Rev. *E  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised September 24,  
1234567...12

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