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CY62157DV20LL-55BVI PDF预览

CY62157DV20LL-55BVI

更新时间： 2024-11-24 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 174K
描述
8M (512K x 16) Static RAM

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CY62157DV20LL-55BVI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：6 X 8 MM, 1 MM HEIGHT, VFBGA-48针数：48
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.48
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e0
长度：8 mm内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：1.8/2 V
认证状态：Not Qualified座面最大高度：1 mm
最大待机电流：0.000003 A最小待机电流：1 V
子类别：SRAMs最大压摆率：0.02 mA
最大供电电压 (Vsup)：2.2 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：6 mm
Base Number Matches：1

CY62157DV20LL-55BVI 数据手册

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CY62157DV20  
MoBL2  
8M (512K x 16) Static RAM  
deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2)  
LOW or both BHE and BLE are HIGH. The input/output pins  
(I/O0 through I/O15) are placed in a high-impedance state  
when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable  
2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH)  
or during a write operation (Chip Enable 1 (CE1) LOW and  
Chip Enable 2 (CE2) HIGH and WE LOW).  
Features  
• Very high speed: 55 ns  
• Wide voltage range: 1.65V to 2.2V  
• Pin compatible with CY62157CV18  
• Ultra low active power  
— Typical active current: 1 mA @ f = 1 MHz  
— Typical active current: 10 mA @ f = fmax  
• Ultra low standby power  
• Easy memory expansion with CE1, CE2 and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered in a 48-ball FBGA  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable  
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7), is written into the location  
specified on the address pins (A0 through A18). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A18).  
Functional Description[1]  
Reading from the device is accomplished by taking Chip  
Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and  
Output Enable (OE) LOW while forcing the Write Enable (WE)  
HIGH. If Byte Low Enable (BLE) is LOW, then data from the  
memory location specified by the address pins will appear on  
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory will appear on I/O8 to I/O15. See the truth table at the  
back of this data sheet for a complete description of read and  
write modes.  
The CY62157DV20 is a high-performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life (MoBL ) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
A 3  
512K x 16  
RAM ARRAY  
2048 x 256 x 16  
I/O0–I/O7  
I/O8–I/O15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BHE  
WE  
CE  
2
CE  
1
OE  
BLE  
Po we r - d o wn  
Circ uit  
CE  
2
BHE  
BLE  
CE  
1
Note:  
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05136 Rev. *B  
Revised March 17, 2003  
1234567...10

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