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CY62157DV30L-55BVI PDF预览

CY62157DV30L-55BVI

更新时间： 2024-11-23 22:36:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 444K
描述
8-Mbit (512K x 16) MoBL Static RAM

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CY62157DV30L-55BVI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA,
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.55
最长访问时间：55 nsJESD-30 代码：R-PBGA-B48
JESD-609代码：e0长度：8 mm
内存密度：8388608 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX16
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
认证状态：Not Qualified座面最大高度：1 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：6 mm
Base Number Matches：1

CY62157DV30L-55BVI 数据手册

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CY62157DV30  
MoBL®  
8-Mbit (512K x 16) MoBLStatic RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C (Preliminary)  
• Very high speed: 45 ns, 55 ns and 70 ns  
• Wide voltage range: 2.20V – 3.60V  
The CY62157DV30 is a high-performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL®) in  
portable applications such as cellular telephones.The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can also be put into  
• Pin-compatible with CY62157CV25, CY62157CV30, and  
standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH and WE LOW).  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A18). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A18).  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table for a complete description  
of read and write modes.  
CY62157CV33  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 12 mA @ f = fmax  
• Ultra-low standby power  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Packages offered: 48-ball BGA, 48-pin TSOPI, and  
44-pin TSOPII  
Logic Block Diagram  
DATA-IN DRIVERS  
A
A
A
A
A
A
A
10  
9
8
7
512K × 16  
RAM Array  
6
5
I/O0 – I/O7  
4
3
2
I/O8 – I/O15  
A
A
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
1
2
CE  
OE  
BLE  
Power-down  
Circuit  
Notes:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-05392 Rev. *E  
Revised August 24, 2004  
1234567...12

中文翻译

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