5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> CY62157DV30LL-55BVXA
CY62157DV30LL-55BVXA PDF预览

CY62157DV30LL-55BVXA

更新时间： 2024-11-24 03:23:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 578K
描述
8-Mbit (512K x 16) MoBL㈢ Static RAM

阅读下载

中文翻译

获取价格

CY62157DV30LL-55BVXA 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.54
最长访问时间：55 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8 mm内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1 mm
最大待机电流：0.000008 A最小待机电流：2 V
子类别：SRAMs最大压摆率：0.015 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：6 mm
Base Number Matches：1

CY62157DV30LL-55BVXA 数据手册

 浏览型号CY62157DV30LL-55BVXA的Datasheet PDF文件第2页浏览型号CY62157DV30LL-55BVXA的Datasheet PDF文件第3页浏览型号CY62157DV30LL-55BVXA的Datasheet PDF文件第4页浏览型号CY62157DV30LL-55BVXA的Datasheet PDF文件第5页浏览型号CY62157DV30LL-55BVXA的Datasheet PDF文件第6页浏览型号CY62157DV30LL-55BVXA的Datasheet PDF文件第7页 
CY62157DV30 MoBL®  
8-Mbit (512K x 16) MoBL® Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62157DV30 is a high-performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones.The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can also be put into  
standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH and WE LOW).  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62157CV25, CY62157CV30, and  
CY62157CV33  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 12 mA @ f = fmax  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A18). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A18).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in Pb-free and non Pb-free 48-ball FBGA,  
44-pin TSOPII, and Pb-free 48-pin TSOPI  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table for a complete description  
of read and write modes.  
Logic Block Diagram  
DATA-IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
512K × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05392 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 8, 2006  
1234567...12

中文翻译

下载PDF

CY62157DV30LL-55BVXA 替代型号

型号 品牌 替代类型 描述 数据表
CY62157EV30LL-45BVXA CYPRESS

完全替代

 8-Mbit (512K x 16) Static RAM

与CY62157DV30LL-55BVXA相关器件

型号 品牌 获取价格 描述 数据表
CY62157DV30LL-55BVXI CYPRESS

获取价格

 		8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-55BVXIT CYPRESS

获取价格

 		Standard SRAM, 512KX16, 55ns, CMOS, PBGA48,
CY62157DV30LL-55ZSI CYPRESS

获取价格

 		8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-55ZSIT CYPRESS

获取价格

 		暂无描述
CY62157DV30LL-55ZSXI CYPRESS

获取价格

 		8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-55ZSXIT CYPRESS

获取价格

 		Standard SRAM, 512KX16, 55ns, CMOS, PDSO44,
CY62157DV30LL-55ZXI CYPRESS

获取价格

 		8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-70BVI CYPRESS

获取价格

 		8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-70BVIT CYPRESS

获取价格

 		Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62157DV30LL-70BVXI CYPRESS

获取价格

 		8-Mbit (512K x 16) MoBL Static RAM

与CY62157DV30LL-55BVXA相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证