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CY62157ELL-45ZSXIT PDF预览

CY62157ELL-45ZSXIT

更新时间： 2024-11-28 14:54:31
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
19页 531K
描述
Asynchronous SRAM

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CY62157ELL-45ZSXIT 数据手册

 浏览型号CY62157ELL-45ZSXIT的Datasheet PDF文件第2页浏览型号CY62157ELL-45ZSXIT的Datasheet PDF文件第3页浏览型号CY62157ELL-45ZSXIT的Datasheet PDF文件第4页浏览型号CY62157ELL-45ZSXIT的Datasheet PDF文件第5页浏览型号CY62157ELL-45ZSXIT的Datasheet PDF文件第6页浏览型号CY62157ELL-45ZSXIT的Datasheet PDF文件第7页 
CY62157E MoBL®  
8-Mbit (512 K × 16) Static RAM  
8-Mbit (512  
K × 16) Static RAM  
when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE  
are HIGH). The input or output pins (I/O0 through I/O15) are  
placed in a high impedance state when:  
Features  
■ Very high speed: 45 ns  
❐ Industrial: –40 °C to +85 °C  
❐ Automotive-E: –40 °C to +125 °C  
■ Deselected (CE1HIGH or CE2 LOW)  
■ Outputs are disabled (OE HIGH)  
■ Wide voltage range: 4.5 V–5.5 V  
■ Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH)  
■ Ultra low standby power  
❐ Typical standby current: 2 A  
❐ Maximum standby current: 8 A (Industrial)  
■ Write operation is active (CE1 LOW, CE2 HIGH and WE LOW)  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0 through  
■ Ultra low active power  
❐ Typical active current: 1.8 mA at f = 1 MHz  
■ Ultra low standby power  
A
18). If Byte High Enable (BHE) is LOW, then data from I/O pins  
■ Easy memory expansion with CE1, CE2 and OE features  
■ Automatic power down when deselected  
■ CMOS for optimum speed and power  
(I/O8 through I/O15) is written into the location specified on the  
address pins (A0 through A18).  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appear  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See Truth Table on page 12  
for a complete description of read and write modes.  
■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA  
package  
Functional Description  
The CY62157E is a high performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications. The device also has an automatic power down  
feature that significantly reduces power consumption when  
addresses are not toggling. Place the device into standby mode  
The CY62157E device is suitable for interfacing with processors  
that have TTL I/P levels. It is not suitable for processors that  
require CMOS I/P levels. Please see Electrical Characteristics  
on page 4 for more details and suggested alternatives.  
For a complete list of related documentation, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A
10  
A
A
9
8
7
A
A
A
A
A
6
5
4
3
512K x 16  
RAM Array  
I/O –I/O  
0
7
I/O –I/O  
8
15  
A
A
A
2
1
0
COLUMN DECODER  
CE  
CE  
2
1
BHE  
WE  
PowerDown  
Circuit  
CE  
CE  
2
BHE  
BLE  
1
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05695 Rev. *N  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 9, 2017  
1234567...19

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