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CY62157EV30_09

更新时间： 2024-11-27 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
15页 401K
描述
8 Mbit (512K x 16) Static RAM

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CY62157EV30_09 数据手册

 浏览型号CY62157EV30_09的Datasheet PDF文件第2页浏览型号CY62157EV30_09的Datasheet PDF文件第3页浏览型号CY62157EV30_09的Datasheet PDF文件第4页浏览型号CY62157EV30_09的Datasheet PDF文件第5页浏览型号CY62157EV30_09的Datasheet PDF文件第6页浏览型号CY62157EV30_09的Datasheet PDF文件第7页 
CY62157EV30 MoBL®  
8 Mbit (512K x 16) Static RAM  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Place the device  
into standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input or output pins (IO0  
through IO15) are placed in a high impedance state when the  
device is deselected (CE1HIGH or CE2 LOW), the outputs are  
disabled (OE HIGH), Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or a write operation is active (CE1  
LOW, CE2 HIGH and WE LOW).  
Features  
■
■
■
TSOP I Package Configurable as 512K x 16 or 1M x 8 SRAM  
High Speed: 45 ns  
Temperature Ranges  
❐
❐
❐
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
Automotive-E: –40°C to +125°C  
■
■
■
Wide Voltage Range: 2.20V to 3.60V  
Pin Compatible with CY62157DV30  
Ultra Low Standby Power  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from IO pins (IO0 through IO7) is written  
into the location specified on the address pins (A0 through A18).  
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8  
through IO15) is written into the location specified on the address  
pins (A0 through A18).  
❐
Typical standby current: 2 μA  
❐
Maximum standby current: 8 μA (Industrial)  
■
Ultra Low Active Power  
Typical active current: 1.8 mA at f = 1 MHz  
❐
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appear  
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO8 to IO15. See the Truth Table on page 10  
for a complete description of read and write modes.  
■
■
■
■
Easy Memory Expansion with CE1, CE2, and OE Features  
Automatic Power Down when Deselected  
CMOS for Optimum Speed and Power  
Available in Pb-free and non Pb-free 48-Ball VFBGA, Pb-free  
44-Pin TSOP II and 48-Pin TSOP I Packages  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Functional Description  
The CY62157EV30 is a high performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A 9  
A 8  
A 7  
A 6  
A 5  
A 4  
512K × 16/1M x 8  
RAM Array  
IO0–IO7  
A 3  
IO8–IO15  
A 2  
A 1  
A 0  
COLUMN DECODER  
BYTE  
CE2  
CE  
BHE  
WE  
1
PowerDown  
Circuit  
CE2  
CE  
BHE  
BLE  
1
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05445 Rev. *F  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised June 26, 2009  
[+] Feedback  
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