Datasheet > CY62157E_13

CY62157E_13

更新时间： 2024-11-24 12:52:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	506K
描述
8-Mbit (512 K x 16) Static RAM

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CY62157E_13 数据手册

CY62157E MoBL^®

8-Mbit (512 K × 16) Static RAM

8-Mbit (512

K × 16) Static RAM

addresses are not toggling. Place the device into standby mode

when deselected (CE₁HIGH or CE₂LOW or both BHE and BLE

are HIGH). The input or output pins (I/O₀through I/O₁₅) are

placed in a high impedance state when:

Features

■ Very high speed: 45 ns

❐ Industrial: –40 °C to +85 °C

❐ Automotive-E: –40 °C to +125 °C

■ Deselected (CE₁HIGH or CE₂LOW)

■ Outputs are disabled (OE HIGH)

■ Wide voltage range: 4.5 V–5.5 V

■ Ultra low standby power

■ Both Byte High Enable and Byte Low Enable are disabled

❐ Typical standby current: 2 A

❐ Maximum standby current: 8 A (Industrial)

(BHE, BLE HIGH)

■ Write operation is active (CE₁LOW, CE₂HIGH and WE LOW)

■ Ultra low active power

❐ Typical active current: 1.8 mA at f = 1 MHz

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀through

₁₈). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O₈through I/O₁₅) is written into the location specified on the

address pins (A₀through A₁₈).

■ Ultra low standby power

■ Easy memory expansion with CE₁, CE₂and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appear

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See Truth Table on page 12

for a complete description of read and write modes.

■ Available in Pb-free 44-pin TSOP II and 48-ball VFBGA

package

Functional Description

The CY62157E is a high performance CMOS static RAM

organized as 512K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life (MoBL^®) in portable

applications. The device also has an automatic power down

feature that significantly reduces power consumption when

The CY62157E device is suitable for interfacing with processors

that have TTL I/P levels. It is not suitable for processors that

require CMOS I/P levels. Please see Electrical Characteristics

on page 4 for more details and suggested alternatives.

Logic Block Diagram

DATA IN DRIVERS

512K x 16

RAM Array

I/O –I/O

COLUMN DECODER

CE₂

CE₁

BHE

PowerDown

Circuit

CE₂

CE₁

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05695 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 5, 2013

12 3 4 5 6 7...18

中文翻译

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与CY62157E_13相关器件

型号	品牌	获取价格	描述	数据表
CY62157ELL-45ZSXI	CYPRESS	获取价格	8-Mbit (512K x 16) Static RAM
CY62157ELL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62157ELL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62157ELL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62157ELL-55BVXE	CYPRESS	获取价格	8-Mbit (512K x 16) Static RAM
CY62157ELL-55BVXE	INFINEON	获取价格	Asynchronous SRAM
CY62157ELL-55BVXET	CYPRESS	获取价格	暂无描述
CY62157ELL-55BVXET	INFINEON	获取价格	Asynchronous SRAM
CY62157ELL-55ZSXE	CYPRESS	获取价格	8-Mbit (512K x 16) Static RAM
CY62157ELL-55ZSXE	INFINEON	获取价格	Asynchronous SRAM

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