5秒后页面跳转
CY62157DV30LL-70BVXIT PDF预览

CY62157DV30LL-70BVXIT

更新时间: 2024-11-25 09:52:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 1986K
描述
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48

CY62157DV30LL-70BVXIT 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:VFBGA,针数:48
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.83
最长访问时间:70 nsJESD-30 代码:R-PBGA-B48
JESD-609代码:e1长度:8 mm
内存密度:8388608 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:48字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX16封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
宽度:6 mm

CY62157DV30LL-70BVXIT 数据手册

 浏览型号CY62157DV30LL-70BVXIT的Datasheet PDF文件第2页浏览型号CY62157DV30LL-70BVXIT的Datasheet PDF文件第3页浏览型号CY62157DV30LL-70BVXIT的Datasheet PDF文件第4页浏览型号CY62157DV30LL-70BVXIT的Datasheet PDF文件第5页浏览型号CY62157DV30LL-70BVXIT的Datasheet PDF文件第6页浏览型号CY62157DV30LL-70BVXIT的Datasheet PDF文件第7页 
CY62157DV30 MoBL®  
8-Mbit (512K x 16) MoBL® Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62157DV30 is a high-performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL®) in  
portable applications such as cellular telephones.The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can also be put into  
standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH and WE LOW).  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62157CV25, CY62157CV30, and  
CY62157CV33  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 12 mA @ f = fmax  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A18). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A18).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in Pb-free and non Pb-free 48-ball FBGA,  
44-pin TSOPII, and Pb-free 48-pin TSOPI  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table for a complete description  
of read and write modes.  
Logic Block Diagram  
DATA-IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
512K × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05392 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 8, 2006  
[+] Feedback  

与CY62157DV30LL-70BVXIT相关器件

型号 品牌 获取价格 描述 数据表
CY62157DV30LL-70ZSI CYPRESS

获取价格

8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-70ZSXI CYPRESS

获取价格

8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30LL-70ZXI CYPRESS

获取价格

8-Mbit (512K x 16) MoBL Static RAM
CY62157E CYPRESS

获取价格

8-Mbit (512K x 16) Static RAM
CY62157E_09 CYPRESS

获取价格

8-Mbit (512K x 16) Static RAM
CY62157E_11 CYPRESS

获取价格

8-Mbit (512 K x 16) Static RAM Automatic power down when deselected
CY62157E_13 CYPRESS

获取价格

8-Mbit (512 K x 16) Static RAM
CY62157ELL-45ZSXI CYPRESS

获取价格

8-Mbit (512K x 16) Static RAM
CY62157ELL-45ZSXI INFINEON

获取价格

Asynchronous SRAM
CY62157ELL-45ZSXIT CYPRESS

获取价格

Standard SRAM, 512KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44