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CY62157DV30LL-55BVXIT PDF预览

CY62157DV30LL-55BVXIT

更新时间： 2024-11-27 19:56:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 573K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48,

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CY62157DV30LL-55BVXIT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：ObsoleteReach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.82最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e1内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3端子数量：48
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：FBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, FINE PITCH
并行/串行：PARALLEL电源：2.5/3.3 V
认证状态：Not Qualified最大待机电流：0.000004 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.015 mA表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
Base Number Matches：1

CY62157DV30LL-55BVXIT 数据手册

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CY62157DV30 MoBL®  
8-Mbit (512K x 16) MoBL® Static RAM  
Features  
Functional Description[1]  
• Temperature Ranges  
The CY62157DV30 is a high-performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones.The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can also be put into  
standby mode when deselected (CE1 HIGH or CE2 LOW or  
both BHE and BLE are HIGH). The input/output pins (I/O0  
through I/O15) are placed in a high-impedance state when:  
deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE  
HIGH), both Byte High Enable and Byte Low Enable are  
disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH and WE LOW).  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• Very high speed: 45 ns  
• Wide voltage range: 2.20V–3.60V  
• Pin-compatible with CY62157CV25, CY62157CV30, and  
CY62157CV33  
• Ultra-low active power  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 12 mA @ f = fmax  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enables  
(CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW.  
If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A18). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A18).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Available in Pb-free and non Pb-free 48-ball FBGA,  
44-pin TSOPII, and Pb-free 48-pin TSOPI  
Reading from the device is accomplished by taking Chip  
Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE)  
LOW while forcing the Write Enable (WE) HIGH. If Byte Low  
Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table for a complete description  
of read and write modes.  
Logic Block Diagram  
DATA-IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
512K × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE2  
CE  
1
OE  
BLE  
Power-down  
Circuit  
Note:  
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05392 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 8, 2006  
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