Datasheet > 存储 > SRAM> CY62157DV30L-45ZSXI

CY62157DV30L-45ZSXI

更新时间： 2024-11-23 22:06:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	444K
描述
8-Mbit (512K x 16) MoBL Static RAM

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CY62157DV30

MoBL^®

8-Mbit (512K x 16) MoBL^Static RAM

Features

Functional Description^[1]

• Temperature Ranges

— Industrial: –40°C to 85°C

— Automotive: –40°C to 125°C (Preliminary)

• Very high speed: 45 ns, 55 ns and 70 ns

• Wide voltage range: 2.20V – 3.60V

The CY62157DV30 is a high-performance CMOS static RAM

organized as 512K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life (MoBL^®) in

portable applications such as cellular telephones.The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can also be put into

• Pin-compatible with CY62157CV25, CY62157CV30, and

standby mode when deselected (CE₁HIGH or CE₂LOW or

both BHE and BLE are HIGH). The input/output pins (I/O₀

through I/O₁₅) are placed in a high-impedance state when:

deselected (CE₁HIGH or CE₂LOW), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are

disabled (BHE, BLE HIGH), or during a write operation (CE₁

LOW, CE₂HIGH and WE LOW).

Writing to the device is accomplished by taking Chip Enables

(CE₁LOW and CE₂HIGH) and Write Enable (WE) input LOW.

If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀

through I/O₇), is written into the location specified on the

address pins (A₀through A₁₈). If Byte High Enable (BHE) is

LOW, then data from I/O pins (I/O₈through I/O₁₅) is written into

the location specified on the address pins (A₀through A₁₈).

Reading from the device is accomplished by taking Chip

Enables (CE₁LOW and CE₂HIGH) and Output Enable (OE)

LOW while forcing the Write Enable (WE) HIGH. If Byte Low

Enable (BLE) is LOW, then data from the memory location

specified by the address pins will appear on I/O₀to I/O₇. If Byte

High Enable (BHE) is LOW, then data from memory will appear

on I/O₈to I/O₁₅. See the truth table for a complete description

of read and write modes.

CY62157CV33

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 12 mA @ f = f_max

• Ultra-low standby power

• Easy memory expansion with CE₁, CE₂, and OE

features

• Automatic power-down when deselected

• CMOS for optimum speed/power

• Packages offered: 48-ball BGA, 48-pin TSOPI, and

44-pin TSOPII

Logic Block Diagram

DATA-IN DRIVERS

512K × 16

RAM Array

I/O0 – I/O7

I/O8 – I/O15

COLUMN DECODER

BHE

BLE

Power-down

Circuit

Notes:

1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, which is available at http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05392 Rev. *E

Revised August 24, 2004

12 3 4 5 6 7...12

中文翻译

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与CY62157DV30L-45ZSXI相关器件

型号	品牌	获取价格	描述	数据表
CY62157DV30L-45ZXI	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30L-55BVE	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30L-55BVI	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30L-55BVIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62157DV30L-55BVXE	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL㈢ Static RAM
CY62157DV30L-55BVXI	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30L-55ZSI	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30L-55ZSIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62157DV30L-55ZSXE	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM
CY62157DV30L-55ZSXI	CYPRESS	获取价格	8-Mbit (512K x 16) MoBL Static RAM

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