Datasheet > CY62157CV25

CY62157CV25

更新时间： 2024-11-23 22:22:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	280K
描述
512K x 16 Static RAM

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中文翻译

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数据手册

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CY62157CV25 数据手册

CY62157CV25/30/33

MoBL™

512K x 16 Static RAM

reducing power consumption by more than 99% when dese-

lected (CE₁HIGH or CE₂LOW or both BLE and BHE are

HIGH). The input/output pins (I/O₀through I/O₁₅) are placed

in a high-impedance state when: deselected (CE₁HIGH or

CE₂LOW), outputs are disabled (OE HIGH), both Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH),

or during a write operation (CE₁LOW and CE₂HIGH and WE

LOW).

Features

• High speed

— 55 ns and 70 ns availability

• Voltage range:

— CY62157CV25: 2.2V–2.7V

— CY62157CV30: 2.7V–3.3V

— CY62157CV33: 3.0V–3.6V

• Ultra-low active power

— Typical active current: 1.5 mA @ f = 1 MHz

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2

(CE₂) HIGH. If Byte Low Enable (BLE) is LOW, then data from

I/O pins (I/O₀through I/O₇), is written into the location speci-

fied on the address pins (A₀through A₁₈). If Byte High Enable

(BHE) is LOW, then data from I/O pins (I/O₈through I/O₁₅) is

written into the location specified on the address pins (A₀

through A₁₈).

— Typicalactivecurrent:5.5mA@f=f_max(70nsspeed)

• Low standby power

• Easy memory expansion with CE₁, CE₂and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable 1 (CE₁) and Output Enable (OE) LOW and Chip Enable

2 (CE₂) HIGH while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins will appear on I/O₀to

I/O₇. If Byte High Enable (BHE) is LOW, then data from mem-

ory will appear on I/O₈to I/O₁₅. See the truth table at the back

of this data sheet for a complete description of read and write

modes.

Functional Description

The CY62157CV25/30/33 are high-performance CMOS static

RAMs organized as 512K words by 16 bits. These devices

feature advanced circuit design to provide ultra-low active cur-

rent. This is ideal for providing More Battery Life™ (MoBL™)

in portable applications such as cellular telephones. The de-

vices also have an automatic power-down feature that signifi-

cantly reduces power consumption by 80% when addresses

are not toggling. The device can also be put into standby mode

The CY62157CV25/30/33 are available in a 48-ball FBGA

package.

Logic Block Diagram

DATA IN DRIVERS

512K × 16

RAM Array

2048 × 4096

I/O –I/O

COLUMN DECODER

BHE

BLE

Power-down

Circuit

BHE

BLE

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05014 Rev. *C

Revised April 23, 2002

12 3 4 5 6 7...13

中文翻译

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与CY62157CV25相关器件

型号	品牌	获取价格	描述	数据表
CY62157CV25LL-55BAI	CYPRESS	获取价格	Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV25LL-70BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV25LL-70BAIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV30LL-55BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV30LL-55BAI	ROCHESTER	获取价格	512KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30LL-70BAE	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV30LL-70BAET	CYPRESS	获取价格	暂无描述
CY62157CV30LL-70BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV30LL-70BAI	ROCHESTER	获取价格	512KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48

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