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CY62156ESL-45BVXI

更新时间： 2024-01-16 07:51:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 491K
描述
8-Mbit (512 K x 16) Static RAM

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中文翻译

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CY62156ESL-45BVXI 技术参数

是否Rohs认证： 符合生命周期：Active
包装说明：VFBGA,Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.76
最长访问时间：45 ns其他特性：IT ALSO OPERATES IN 2.2V MINIMUM
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8 mm内存密度：8388608 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260座面最大高度：1 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：40宽度：6 mm
Base Number Matches：1

CY62156ESL-45BVXI 数据手册

 浏览型号CY62156ESL-45BVXI的Datasheet PDF文件第2页浏览型号CY62156ESL-45BVXI的Datasheet PDF文件第3页浏览型号CY62156ESL-45BVXI的Datasheet PDF文件第4页浏览型号CY62156ESL-45BVXI的Datasheet PDF文件第5页浏览型号CY62156ESL-45BVXI的Datasheet PDF文件第6页浏览型号CY62156ESL-45BVXI的Datasheet PDF文件第7页 
CY62156ESL MoBL®  
8-Mbit (512 K × 16) Static RAM  
8-Mbit (512  
K × 16) Static RAM  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Place the device  
in standby mode when deselected (CE1 HIGH or CE2 LOW). The  
input or output pins (I/O0 through I/O15) are placed in a high  
impedance state when the device is deselected (CE1 HIGH or  
CE2 LOW), the outputs are disabled (OE HIGH), Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or  
a write operation is active (CE1 LOW, CE2 HIGH and WE LOW).  
Features  
■ High Speed: 45 ns  
■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V  
■ Ultra Low Standby Power  
❐ Typical standby current: 2 A  
❐ Maximum standby current: 8 A  
■ Ultra Low Active Power  
❐ Typical active current: 1.8 mA at f = 1 MHz  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is  
written into the location specified on the address pins (A0 through  
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(I/O8 through I/O15) is written into the location specified on the  
address pins (A0 through A18).  
■ Easy Memory Expansion with CE1, CE2, and OE Features  
■ Automatic Power Down when Deselected  
■ CMOS for Optimum Speed and Power  
■ Available in Pb-free 48-ball very fine-pitch ball grid array  
(VFBGA) packages  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appear  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See the Truth Table on page  
11 for a complete description of read and write modes.  
Functional Description  
The CY62156ESL is a high performance CMOS static RAM  
organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
512 K × 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-54995 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised May 13, 2013  
1234567...16

中文翻译

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