Datasheet > CY62157BV18LL-70BAI

CY62157BV18LL-70BAI

更新时间： 2024-09-26 10:00:03

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
9页	132K
描述
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, FBGA-48

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CY62157BV18LL

MoBL2™

ADVANCE INFORMATION

512K x 16 Static RAM

through I/O ) are placed in a high-impedance state when:

Features

deselected (CE HIGH), outputs are disabled (OE HIGH), BHE

and BLE are disabled (BHE, BLE HIGH), or during a write

operation (CE LOW and WE LOW).

• Low voltage range:

— CY62157BV18LL: 1.65V–1.95V

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

• Ultra-low active, standby power

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

(BLE) is LOW, then data from I/O pins (I/O through I/O ), is

written into the location specified on the address pins (A

through A ). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O through I/O ) is written into the location

specified on the address pins (A through A ).

Functional Description

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

The CY62157BV18LL is a high-performance CMOS static

RAM organized as 512K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL™) in por-

table applications such as cellular telephones. The device also

has an automatic power-down feature that significantly reduc-

es power consumption by 99% when addresses are not tog-

gling. The device can also be put into standby mode when

will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O to I/O . See the

truth table at the back of this datasheet for a complete descrip-

tion of read and write modes.

The CY62157BV18LL is available in a 48-Ball FBGA package.

deselected (CE HIGH, CS2 LOW). The input/output pins (I/O

Logic Block Diagram

DATA IN DRIVERS

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

256K x 16

RAM Array

1024 X 4096

I/O₀– I/O₇

I/O₈– I/O₁₅

A₁

A₀

COLUMN DECODER

BHE

CEx

BLE

CEx is the combination of CE and CS2

62157V–1

MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 23, 2000

12 3 4 5 6 7...9

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与CY62157BV18LL-70BAI相关器件

型号	品牌	获取价格	描述	数据表
CY62157CV18	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV18LL-55BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV18LL-70BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV25	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV25LL-55BAI	CYPRESS	获取价格	Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV25LL-70BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV25LL-70BAIT	CYPRESS	获取价格	Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48
CY62157CV30	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV30LL-55BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV30LL-55BAI	ROCHESTER	获取价格	512KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48

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