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CY62157BV18LL-55BAI PDF预览

CY62157BV18LL-55BAI

更新时间： 2024-11-24 14:48:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
9页 132K
描述
Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, FBGA-48

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CY62157BV18LL-55BAI 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA-48针数：48
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.78
Is Samacsys：N最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e0长度：10 mm
内存密度：8388608 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：524288 words
字数代码：512000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：512KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：1.8 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.000005 A最小待机电流：1 V
子类别：SRAMs最大压摆率：0.015 mA
最大供电电压 (Vsup)：1.95 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：6 mm
Base Number Matches：1

CY62157BV18LL-55BAI 数据手册

 浏览型号CY62157BV18LL-55BAI的Datasheet PDF文件第2页浏览型号CY62157BV18LL-55BAI的Datasheet PDF文件第3页浏览型号CY62157BV18LL-55BAI的Datasheet PDF文件第4页浏览型号CY62157BV18LL-55BAI的Datasheet PDF文件第5页浏览型号CY62157BV18LL-55BAI的Datasheet PDF文件第6页浏览型号CY62157BV18LL-55BAI的Datasheet PDF文件第7页 
CY62157BV18LL  
MoBL2™  
ADVANCE INFORMATION  
512K x 16 Static RAM  
through I/O ) are placed in a high-impedance state when:  
Features  
15  
deselected (CE HIGH), outputs are disabled (OE HIGH), BHE  
and BLE are disabled (BHE, BLE HIGH), or during a write  
operation (CE LOW and WE LOW).  
• Low voltage range:  
— CY62157BV18LL: 1.65V–1.95V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
18  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
18  
Functional Description  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
The CY62157BV18LL is a high-performance CMOS static  
RAM organized as 512K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL™) in por-  
table applications such as cellular telephones. The device also  
has an automatic power-down feature that significantly reduc-  
es power consumption by 99% when addresses are not tog-  
gling. The device can also be put into standby mode when  
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,  
0
7
then data from memory will appear on I/O to I/O . See the  
8
15  
truth table at the back of this datasheet for a complete descrip-  
tion of read and write modes.  
The CY62157BV18LL is available in a 48-Ball FBGA package.  
deselected (CE HIGH, CS2 LOW). The input/output pins (I/O  
0
Logic Block Diagram  
DATA IN DRIVERS  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
256K x 16  
RAM Array  
1024 X 4096  
I/O0 – I/O7  
I/O8 – I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CEx  
OE  
BLE  
CEx is the combination of CE and CS2  
62157V–1  
MoBL, MoBL2, and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
March 23, 2000  
1234567...9

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