Datasheet > CY62156ESL

CY62156ESL

更新时间： 2024-11-24 12:27:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	491K
描述
8-Mbit (512 K x 16) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62156ESL 数据手册

CY62156ESL MoBL^®

8-Mbit (512 K × 16) Static RAM

8-Mbit (512

K × 16) Static RAM

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Place the device

in standby mode when deselected (CE₁HIGH or CE₂LOW). The

input or output pins (I/O₀through I/O₁₅) are placed in a high

impedance state when the device is deselected (CE₁HIGH or

CE₂LOW), the outputs are disabled (OE HIGH), Byte High

Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or

a write operation is active (CE₁LOW, CE₂HIGH and WE LOW).

Features

■ High Speed: 45 ns

■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V

■ Ultra Low Standby Power

❐ Typical standby current: 2 A

❐ Maximum standby current: 8 A

■ Ultra Low Active Power

❐ Typical active current: 1.8 mA at f = 1 MHz

To write to the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇) is

written into the location specified on the address pins (A₀through

A₁₈). If Byte High Enable (BHE) is LOW, then data from I/O pins

(I/O₈through I/O₁₅) is written into the location specified on the

address pins (A₀through A₁₈).

■ Easy Memory Expansion with CE₁, CE₂, and OE Features

■ Automatic Power Down when Deselected

■ CMOS for Optimum Speed and Power

■ Available in Pb-free 48-ball very fine-pitch ball grid array

(VFBGA) packages

To read from the device, take Chip Enable (CE₁LOW and CE₂

HIGH) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data

from the memory location specified by the address pins appear

on I/O₀to I/O₇. If Byte High Enable (BHE) is LOW, then data from

memory appears on I/O₈to I/O₁₅. See the Truth Table on page

11 for a complete description of read and write modes.

Functional Description

The CY62156ESL is a high performance CMOS static RAM

organized as 512K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life (MoBL^®) in portable

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

512 K × 16

RAM Array

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 001-54995 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 13, 2013

12 3 4 5 6 7...16

中文翻译

下载PDF

与CY62156ESL相关器件

型号	品牌	获取价格	描述	数据表
CY62156ESL-45BVXI	CYPRESS	获取价格	8-Mbit (512 K x 16) Static RAM
CY62156ESL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62156ESL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62157BV18LL-55BAI	CYPRESS	获取价格	Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, FBGA-48
CY62157BV18LL-70BAI	CYPRESS	获取价格	Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, FBGA-48
CY62157CV18	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV18LL-55BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV18LL-70BAI	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV25	CYPRESS	获取价格	512K x 16 Static RAM
CY62157CV25LL-55BAI	CYPRESS	获取价格	Standard SRAM, 512KX16, 55ns, CMOS, PBGA48, 6 X 10 MM, 1.20 MM HEIGHT, FBGA-48

与CY62156ESL相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

38
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

30
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

58
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

54

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62156ESL

CY62156ESL 数据手册

与CY62156ESL相关器件

与CY62156ESL相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62156ESL

CY62156ESL 数据手册

与CY62156ESL相关器件

与CY62156ESL相关文章

您还可以找

您在本页遇到什么问题？