Datasheet > 存储 > SRAM> CY62148VLL-70BAI

CY62148VLL-70BAI

更新时间： 2024-09-23 22:15:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	191K
描述
512K x 8 MoBL Static RAM

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中文翻译

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数据手册

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CY62148VLL-70BAI 数据手册

MoBL

CY62148V MoBL™

512K x 8 MoBL Static RAM

The device can be put into standby mode when deselected

(CE HIGH).

Features

• Low voltage range:

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O through I/O ) is then written into the location speci-

— 2.7V–3.6V

• Ultra low active power

• Low standby power

fied on the address pins (A through A ).

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

Functional Description

The eight input/output pins (I/O through I/O ) are placed in a

The CY62148V is a high-performance CMOS static RAM or-

ganized as 524,288 words by 8 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL™) in portable

applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces

power consumption by 99% when addresses are not toggling.

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII,

and a 32-pin SOIC package.

Logic Block Diagram

I/O

Data in Drivers

I/O

512K x 8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

62148V-1

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Cypress Semiconductor Corporation

March 23, 2000

12 3 4 5 6 7...11

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