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CY62148L-70SI PDF预览

CY62148L-70SI

更新时间: 2024-11-05 04:53:27
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赛普拉斯 - CYPRESS /
页数 文件大小 规格书
7页 189K
描述
512K x 8 Static RAM

CY62148L-70SI 数据手册

 浏览型号CY62148L-70SI的Datasheet PDF文件第2页浏览型号CY62148L-70SI的Datasheet PDF文件第3页浏览型号CY62148L-70SI的Datasheet PDF文件第4页浏览型号CY62148L-70SI的Datasheet PDF文件第5页浏览型号CY62148L-70SI的Datasheet PDF文件第6页浏览型号CY62148L-70SI的Datasheet PDF文件第7页 
1CY62148  
fax id: 1079  
PRELIMINARY  
CY62148  
512K x 8 Static RAM  
an automatic power-down feature that reduces power con-  
sumption by more than 99% when deselected.  
Features  
• 4.5V5.5V operation  
• CMOS for optimum speed/power  
• Low active power  
Writing to the device is accomplished by taking chip enable  
one (CE) and write enable (WE) inputs LOW. Data on the eight  
I/O pins (I/O through I/O ) is then written into the location  
0
7
specified on the address pins (A through A ).  
0
18  
— 660 mW (max.)  
Reading from the device is accomplished by taking chip en-  
able one (CE) and output enable (OE) LOW while forcing write  
enable (WE). Under these conditions, the contents of the  
memory location specified by the address pins will appear on  
the I/O pins.  
• Low standby power (L version)  
— 2.75 mW (max.)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE options  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY62148 is a high-performance CMOS static RAM orga-  
nized as 524,288 words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE), an active LOW  
output enable (OE), and three-state drivers. This device has  
The CY62148 is available in a standard 450-mil-wide body  
width SOIC package.  
Logic Block Diagram  
Pin Configuration  
Top View  
SOIC  
A
A
V
32  
31  
30  
17  
1
CC  
16  
14  
12  
A
A
2
3
4
15  
A
A
18  
29  
28  
WE  
5
A
A
A
A
A
A
7
13  
8
I/O  
27  
26  
0
6
6
INPUT BUFFER  
5
7
9
25  
24  
23  
22  
21  
A
A
3
A
0
8
9
10  
11  
12  
13  
A
4
11  
I/O  
1
A
OE  
1
2
A
A
10  
2
A
A
1
I/O  
CE  
I/O  
I/O  
I/O  
2
A
3
4
A
7
0
A
I/O  
I/O  
I/O  
0
1
2
6
5
4
3
20  
19  
A
I/O  
5
3
14  
15  
16  
512K x 8  
ARRAY  
A
6
I/O  
I/O  
18  
17  
A
GND  
7
A
I/O  
4
8
A9  
A
I/O  
5
10  
I/O  
6
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
7
62148-1  
OE  
Selection Guide  
CY62148–55  
55  
CY62148–70  
70  
Maximum Access Time (ns)  
Maximum Operating Current  
Maximum CMOS Standby Current  
Commercial  
Commercial  
120 mA  
2 mA  
120 mA  
2 mA  
L
0.5 mA  
0.5 mA  
Shaded areas contain advance information  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
December 1996 - Revised July 31, 1997