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CY62148ELL-55SXIT PDF预览

CY62148ELL-55SXIT

更新时间: 2024-11-20 18:27:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
18页 1986K
描述
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, ROHS COMPLIANT, SOIC-32

CY62148ELL-55SXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP32,.56针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:1.24
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32JESD-609代码:e4
长度:20.4465 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP32,.56封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified座面最大高度:2.997 mm
最大待机电流:0.000007 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.02 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:11.303 mm
Base Number Matches:1

CY62148ELL-55SXIT 数据手册

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CY62148E MoBL®  
4-Mbit (512K × 8) Static RAM  
4-Mbit (512K  
× 8) Static RAM  
advanced circuit design to provide ultra low standby current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
applications. The device also has an automatic power-down  
feature that significantly reduces power consumption when  
addresses are not toggling. Placing the device into standby  
mode reduces power consumption by more than 99% when  
deselected (CE HIGH). The eight input and output pins (I/O0  
through I/O7) are placed in a high impedance state when the  
device is deselected (CE HIGH), Outputs are disabled (OE  
HIGH), or during an active Write operation (CE LOW and WE  
LOW).  
Features  
Very high speed: 45 ns  
Voltage range: 4.5 V to 5.5 V  
Pin compatible with CY62148B  
Ultra low standby power  
Typical standby current: 1 µA  
Maximum standby current: 7 µA (Industrial)  
Ultra low active power  
Typical active current: 2.0 mA at f = 1 MHz  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
Easy memory expansion with CE, and OE features  
Automatic power-down when deselected  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appear on the I/O pins.  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
Available in Pb-free 32-pin thin small outline package (TSOP) II  
and 32-pin small-outline integrated circuit (SOIC)[1] packages  
The CY62148E device is suitable for interfacing with processors  
that have TTL I/P levels. It is not suitable for processors that  
require CMOS I/P levels. Please see Electrical Characteristics  
on page 4 for more details and suggested alternatives.  
Functional Description  
The CY62148E is a high performance CMOS static RAM  
organized as 512K words by 8-bits. This device features  
For a complete list of related documentation, click here.  
Logic Block Diagram  
A
I/O  
I
0
0
INPUT BUFFER  
A
1
A
2
I/O  
I
1
2
3
4
5
6
7
A
3
A
4
I/O  
I
A
5
A
I/O  
I
6
512K x 8  
A
7
A
I/O  
I
8
ARRAY  
A
9
A
I/O  
I
10  
A
11  
A
I/O  
I
12  
I/O  
CE  
I
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. SOIC package is available only in 55 ns speed bin.  
Cypress Semiconductor Corporation  
Document Number: 38-05442 Rev. *P  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 1, 2016  
 
 
 

CY62148ELL-55SXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62148ELL-55SXA CYPRESS

完全替代

4-Mbit (512K x 8) Static RAM
CY62148ELL-55SXI CYPRESS

类似代替

4-Mbit (512K x 8) Static RAM
IS62C5128BL-45QLI ISSI

功能相似

Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, PLASTIC, SOP-32

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