5秒后页面跳转
捷配首页

Datasheet > CY62148ESL
CY62148ESL PDF预览

CY62148ESL

更新时间： 2024-01-22 00:33:56
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 324K
描述
4-Mbit (512K x 8) Static RAM

阅读下载

中文翻译

获取价格

CY62148ESL 数据手册

 浏览型号CY62148ESL的Datasheet PDF文件第2页浏览型号CY62148ESL的Datasheet PDF文件第3页浏览型号CY62148ESL的Datasheet PDF文件第4页浏览型号CY62148ESL的Datasheet PDF文件第5页浏览型号CY62148ESL的Datasheet PDF文件第6页浏览型号CY62148ESL的Datasheet PDF文件第7页 
CY62148ESL MoBL®  
4-Mbit (512K x 8) Static RAM  
Features  
Functional Description  
■
■
■
Very high speed: 55 ns  
The CY62148ESL is a high performance CMOS static RAM  
organized as 512K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption. Placing the device into standby mode reduces  
power consumption by more than 99 percent when deselected  
(CE HIGH). The eight input and output pins (IO0 through IO7) are  
placed in a high impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW and WE LOW).  
Wide voltage range: 2.2V to 3.6V and 4.5V to 5.5V  
Ultra low standby power  
❐
Typical standby current: 1 μA  
Maximum standby current: 7 μA  
❐
■
Ultra low active power  
Typical active current: 2 mA at f = 1 MHz  
❐
■
■
■
■
Easy memory expansion with CE and OE features  
Automatic power down when deselected  
CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is  
then written into the location specified on the address pins (A0  
through A18).  
Available in Pb-free 32-pin STSOP package  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appear on the IO pins.  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
0
INPUT BUFFER  
IO  
1
IO  
2
512K x 8  
ARRAY  
IO  
3
IO  
4
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 001-50045 Rev. **  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised January 21, 2009  
[+] Feedback  
1234567...10

中文翻译

下载PDF

与CY62148ESL相关器件

型号 品牌 获取价格 描述 数据表
CY62148ESL_10 CYPRESS

获取价格

 		4-Mbit (512 K × 8) Static RAM
CY62148ESL_11 CYPRESS

获取价格

 		4-Mbit (512 K x 8) Static RAM Automatic power-down when deselected
CY62148ESL-55ZAXA CYPRESS

获取价格

 		4-Mbit (512 K × 8) Static RAM
CY62148ESL-55ZAXAT CYPRESS

获取价格

 		Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
CY62148ESL-55ZAXI CYPRESS

获取价格

 		4-Mbit (512K x 8) Static RAM
CY62148ESL-55ZAXI INFINEON

获取价格

 		Asynchronous SRAM
CY62148ESL-55ZAXIT INFINEON

获取价格

 		Asynchronous SRAM
CY62148EV30 CYPRESS

获取价格

 		4-Mbit (512K x 8) Static RAM
CY62148EV30_09 CYPRESS

获取价格

 		4-Mbit (512K x 8) Static RAM
CY62148EV30_12 CYPRESS

获取价格

 		4-Mbit (512 K × 8) Static RAM

与CY62148ESL相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证