Datasheet > CY62148ESL_10

CY62148ESL_10

更新时间： 2024-02-19 05:12:29

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	359K
描述
4-Mbit (512 K × 8) Static RAM

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CY62148ESL_10 数据手册

CY62148ESL MoBL^®

4-Mbit (512 K × 8) Static RAM

4-Mbit (512

K × 8) Static RAM

Features

Functional Description

■ Higher speed up to 55 ns

The CY62148ESL is a high performance CMOS static RAM

organized as 512 K words by 8-bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power-down feature that significantly reduces power

consumption. Placing the device in standby mode reduces

power consumption by more than 99 percent when deselected

(CE HIGH). The eight input and output pins (I/O₀through I/O₇)

are placed in a high impedance state when the device is

deselected (CE HIGH), the outputs are disabled (OE HIGH), or

during a write operation (CE LOW and WE LOW).

■ Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V

■ Ultra low standby power

❐ Typical standby current: 1 µA

❐ Maximum standby current: 7 µA

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

■ Easy memory expansion with CE and OE features

■ Automatic power-down when deselected

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins (A₀

through A₁₈).

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Available in Pb-free 32-Pin shrunk thin small outline package

(STSOP) package

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the I/O pins.

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

512K x 8

I/O

ARRAY

I/O

POWER

DOWN

COLUMN DECODER

Cypress Semiconductor Corporation

Document #: 001-50045 Rev. *C

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 23, 2010

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与CY62148ESL_10相关器件

型号	品牌	获取价格	描述	数据表
CY62148ESL_11	CYPRESS	获取价格	4-Mbit (512 K x 8) Static RAM Automatic power-down when deselected
CY62148ESL-55ZAXA	CYPRESS	获取价格	4-Mbit (512 K × 8) Static RAM
CY62148ESL-55ZAXAT	CYPRESS	获取价格	Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, LEAD FREE, STSOP-32
CY62148ESL-55ZAXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148ESL-55ZAXI	INFINEON	获取价格	Asynchronous SRAM
CY62148ESL-55ZAXIT	INFINEON	获取价格	Asynchronous SRAM
CY62148EV30	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148EV30_09	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148EV30_12	CYPRESS	获取价格	4-Mbit (512 K Ã 8) Static RAM
CY62148EV30LL	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM

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