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CY62148EV30LL-45ZSXA PDF预览

CY62148EV30LL-45ZSXA

更新时间: 2024-11-05 06:51:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
12页 855K
描述
4-Mbit (512K x 8) Static RAM

CY62148EV30LL-45ZSXA 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:20.95 X 11.76 MM, 1 MM HEIGHT, LEAD FREE, TSOP2-32
针数:32Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.38最长访问时间:45 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e3长度:20.95 mm
内存密度:4194304 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP32,.46
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.000007 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.02 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:20
宽度:10.16 mmBase Number Matches:1

CY62148EV30LL-45ZSXA 数据手册

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MoBL® CY62148EV30  
4-Mbit (512K x 8) Static RAM  
Features  
Functional Description  
Very high speed: 45 ns  
Wide voltage range: 2.20V to 3.60V  
The CY62148EV30[2] is a high performance CMOS static RAM  
organized as 512K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption. Placing the device into standby mode reduces  
power consumption by more than 99 percent when deselected  
(CE HIGH). The eight input and output pins (IO0 through IO7) are  
placed in a high impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW and WE LOW).  
Temperature ranges  
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
Pin compatible with CY62148DV30  
Ultra low standby power  
Typical standby current: 1 μA  
Maximum standby current: 7 μA (Industrial)  
Ultra low active power  
Typical active current: 2 mA at f = 1 MHz  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is  
then written into the location specified on the address pins (A0  
through A18).  
Easy memory expansion with CE, and OE features  
Automatic power down when deselected  
CMOS for optimum speed and power  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appear on the IO pins.  
Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin  
SOIC [1] packages  
Logic Block Diagram  
A
0
IO  
0
INPUT BUFFER  
A
1
A
2
IO  
1
A
3
A
4
IO  
2
A
5
A
6
512K x 8  
ARRAY  
IO  
3
A
A
A
A
A
A
7
8
IO  
4
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Notes  
1. SOIC package is available only in 55 ns speed bin.  
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05576 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 4, 2008  
[+] Feedback  

CY62148EV30LL-45ZSXA 替代型号

型号 品牌 替代类型 描述 数据表
CY62148EV30LL-45ZSXAT CYPRESS

完全替代

Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, LEAD FREE, TSOP2-32
CY62148EV30LL-45ZSXIT CYPRESS

完全替代

Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, LEAD FREE, TSOP2-32
CY62148EV30LL-45ZSXI CYPRESS

完全替代

4-Mbit (512K x 8) Static RAM

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