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CY62148EV30LL-45ZSXI

更新时间： 2024-11-05 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 1007K
描述
4-Mbit (512K x 8) Static RAM

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CY62148EV30LL-45ZSXI 数据手册

 浏览型号CY62148EV30LL-45ZSXI的Datasheet PDF文件第2页浏览型号CY62148EV30LL-45ZSXI的Datasheet PDF文件第3页浏览型号CY62148EV30LL-45ZSXI的Datasheet PDF文件第4页浏览型号CY62148EV30LL-45ZSXI的Datasheet PDF文件第5页浏览型号CY62148EV30LL-45ZSXI的Datasheet PDF文件第6页浏览型号CY62148EV30LL-45ZSXI的Datasheet PDF文件第7页 
CY62148EV30 MoBL®  
4-Mbit (512K x 8) Static RAM  
Functional Description [2]  
Features  
• Very high speed: 45 ns  
The CY62148EV30 is a high performance CMOS static RAM  
organized as 512K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption. Placing the device into standby  
mode reduces power consumption by more than 99% when  
deselected (CE HIGH). The eight input and output pins (IO0  
through IO7) are placed in a high impedance state when the  
device is deselected (CE HIGH), the outputs are disabled (OE  
HIGH), or during a write operation (CE LOW and WE LOW).  
— Wide voltage range: 2.20V – 3.60V  
• Pin compatible with CY62148DV30  
• Ultra low standby power  
— Typical standby current: 1 µA  
— Maximum standby current: 7 µA (Industrial)  
• Ultra low active power  
— Typical active current: 2 mA @ f = 1 MHz  
• Easy memory expansion with CE, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight IO pins (IO0 through IO7)  
is then written into the location specified on the address pins  
(A0 through A18).  
• Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and  
32-pin SOIC [1] packages  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins appear on the IO pins.  
Logic Block Diagram  
A
0
IO  
0
INPUT BUFFER  
A
1
A
2
IO  
1
A
3
A
4
IO  
2
A
5
A
6
512K x 8  
ARRAY  
IO  
3
A
A
A
A
A
A
7
8
IO  
4
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Notes  
1. SOIC package is available only in 55 ns speed bin.  
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05576 Rev. *F  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised April 18, 2007  
[+] Feedback  
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CY62148EV30LL-45ZSXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62148G30-45ZSXI CYPRESS

完全替代

 4-Mbit (512K words × 8 bit) Static RAM with
CY62148EV30LL-45ZSXA CYPRESS

完全替代

 4-Mbit (512K x 8) Static RAM
CY62148EV30LL-45ZSXIT CYPRESS

类似代替

 Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, LEAD FREE, TSOP2-32

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