Datasheet > CY62148EV30_12

CY62148EV30_12

更新时间： 2024-11-05 12:22:51

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	414K
描述
4-Mbit (512 K Ã 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62148EV30_12 数据手册

CY62148EV30 MoBL^®

4-Mbit (512 K × 8) Static RAM

4-Mbit (512

K × 8) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

❐ Wide voltage range: 2.20 V to 3.60 V

The CY62148EV30 is a high performance CMOS static RAM

organized as 512 K words by 8 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption. Placing the device into standby mode reduces

power consumption by more than 99 percent when deselected

(CE HIGH). The eight input and output pins (I/O₀through I/O₇)

are placed in a high impedance state when the device is

deselected (CE HIGH), the outputs are disabled (OE HIGH), or

during a write operation (CE LOW and WE LOW).

■ Temperature range:

❐ Industrial: –40 °C to +85 °C

❐ Automotive-A: –40 °C to +85 °C

■ Pin compatible with CY62148DV30

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 7 A (Industrial)

■ Ultra low active power

❐ Typical active current: 2 mA at f = 1 MHz

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins (A₀

through A₁₈).

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the I/O pins.

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Available in Pb-free 36-ball very fine-pitch ball grid array

(VFBGA), 32-pin thin small outline package (TSOP) II, and

32-pin small outline integrated circuit (SOIC) ^[1]packages

Logic Block Diagram

I/O

INPUT BUFFER

I/O

512K x 8

ARRAY

I/O

POWER

DOWN

COLUMN DECODER

Note

1. SOIC package is available only in 55 ns speed bin.

Cypress Semiconductor Corporation

Document Number: 38-05576 Rev. *O

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised September 4, 2012

12 3 4 5 6 7...18

中文翻译

下载PDF

与CY62148EV30_12相关器件

型号	品牌	获取价格	描述	数据表
CY62148EV30LL	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148EV30LL-45BVI	CYPRESS	获取价格	4-Mbit (512 K Ã 8) Static RAM
CY62148EV30LL-45BVI	INFINEON	获取价格	Asynchronous SRAM
CY62148EV30LL-45BVIT	INFINEON	获取价格	Asynchronous SRAM
CY62148EV30LL-45BVXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62148EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62148EV30LL-45ZSXA	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148EV30LL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, LEAD FREE, TSOP2-32
CY62148EV30LL-45ZSXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM

与CY62148EV30_12相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62148EV30_12

CY62148EV30_12 数据手册

与CY62148EV30_12相关器件

与CY62148EV30_12相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62148EV30_12

CY62148EV30_12 数据手册

与CY62148EV30_12相关器件

与CY62148EV30_12相关文章

您还可以找

您在本页遇到什么问题？