CY62148G MoBL®
4-Mbit (512K words × 8 bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (512K words
× 8 bit) Static RAM with Error-Correcting Code (ECC)
Device is accessed by asserting the chip enable (CE) input LOW.
Data writes are performed by asserting the Write Enable (WE)
input LOW, while providing the data on I/O0 through I/O7 and
address on A0 through A18 pins.
Features
■ High speed: 45 ns/55 ns
■ Ultra-low standby power
Data reads are performed by asserting the Output Enable (OE)
input and providing the required address on the address lines.
Read data is accessible on the I/O lines (I/O0 through I/O7).
❐ Typical standby current: 3.5 A
❐ Maximum standby current: 8.7 A
■ Embedded ECC for single-bit error correction[1]
All I/Os (I/O0 through I/O7) are placed in a HI-Z state when the
device is deselected (CE HIGH or control signal OE is
de-asserted).
■ Wide voltage range: 1.65V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V
■ 1.0-V data retention
See the Truth Table – CY62148G on page 12 for a complete
description of read and write modes.
■ TTL-compatible inputs and outputs
■ Pb-free 32-pin SOIC and 32-pin TSOP II packages
The logic block diagrams are on page 2.
Functional Description
CY62148G is a high-performance CMOS low-power (MoBL)
SRAM device with embedded ECC[1]. This device is offered
multiple pin configurations.
Logic Block Diagram – CY62148G
DATAIN
ECC ENCODER
DRIVERS
A0
A1
A2
A3
A4
A5
I/O0-I/O7
512K x 8
RAM ARRAY
A6
A7
A8
A9
COLUMN DECODER
WE
CE
OE
Note
1. This device does not support automatic write-back on error detection.
Cypress Semiconductor Corporation
Document Number: 001-95415 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2017