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CY62138FLL-45SXI PDF预览

CY62138FLL-45SXI

更新时间: 2024-11-05 03:11:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 841K
描述
2-Mbit (256K x 8) Static RAM

CY62138FLL-45SXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP32,.56针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:2.31最长访问时间:45 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G32
JESD-609代码:e4长度:20.4465 mm
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:32
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:256KX8
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP32,.56
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:2.997 mm最大待机电流:0.000005 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.018 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:11.303 mmBase Number Matches:1

CY62138FLL-45SXI 数据手册

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CY62138F MoBL®  
2-Mbit (256K x 8) Static RAM  
Features  
Functional Description [1]  
• High speed: 45 ns  
The CY62138F is a high performance CMOS static RAM  
organized as 256K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption when addresses are not toggling.  
Placing the device into standby mode reduces power  
consumption by more than 99% when deselected (CE1 HIGH  
or CE2 LOW).  
• Wide voltage range: 4.5 V – 5.5 V  
• Pin compatible with CY62138V  
• Ultra low standby power  
— Typical standby current: 1 µA  
— Maximum standby current: 5 µA  
• Ultra low active power  
— Typical active current: 1.6 mA @ f = 1 MHz  
• Easy memory expansion with CE1, CE2, and OE features  
• Automatic power down when deselected  
• CMOS for optimum speed and power  
To write to the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and Write Enable (WE) inputs LOW. Data on the eight  
IO pins (IO0 through IO7) is then written into the location  
specified on the address pins (A0 through A17).  
• Available in Pb-free 32-pin SOIC and 32-pin TSOP II  
packages  
To read from the device, take Chip Enable (CE1 LOW and CE2  
HIGH) and output enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins appear on  
the IO pins.  
The eight input and output pins (IO0 through IO7) are placed  
in a high impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or  
during a write operation (CE1 LOW and CE2 HIGH and WE  
LOW).  
Logic Block Diagram  
IO  
0
DATA IN DRIVERS  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
1
IO  
2
256K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
9
10  
11  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-13194 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 26, 2007  
[+] Feedback  

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