Datasheet > CY62126EV30_11

CY62126EV30_11

更新时间： 2024-09-13 09:42:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	482K
描述
1-Mbit (64 K x 16) Static RAM Automatic power down when deselected

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62126EV30_11 数据手册

CY62126EV30 MoBL^®

1-Mbit (64 K × 16) Static RAM

1-Mbit (64

K × 16) Static RAM

Features

Functional Description

■ High speed: 45 ns

The CY62126EV30 is a high performance CMOS static RAM

organized as 64K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life(MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device in standby mode reduces power consumption by more

than 99 percent when deselected (CE HIGH). The input and

output pins (I/O₀through I/O₁₅) are placed in a high impedance

state when the device is deselected (CE HIGH), the outputs are

disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH) or during a write

operation (CE LOW and WE LOW).

■ Temperature ranges

❐ Industrial: –40 °C to +85 °C

❐ Automotive: –40 °C to +125 °C

■ Wide voltage range: 2.2 V to 3.6 V

■ Pin compatible with CY62126DV30

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 4 A

■ Ultra low active power

❐ Typical active current: 1.3 mA at f = 1 MHz

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇) is written into the location

specified on the address pins (A₀through A₁₅). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₅).

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Offered in Pb-free 48-ball very fine-pitch ball grid array

(VFBGA) and 44-pin thin small outline package (TSOP) II

packages

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See the Truth Table on page 11 for a

complete description of read and write modes.

Logic Block Diagram

DATA IN DRIVERS

64K x 16

I/O –I/O

RAM Array

I/O –I/O

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05486 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised May 31, 2011

[+] Feedback

12 3 4 5 6 7...18

中文翻译

下载PDF

与CY62126EV30_11相关器件

型号	品牌	获取价格	描述	数据表
CY62126EV30LL	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45BVXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62126EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXA	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126EV30LL-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM

与CY62126EV30_11相关文章

SL74HC10N：高性能三输入与非门解析
2024-09-03

78
AIC1781A 电池充电控制器深度解析
2024-09-03

69
Pickering新高压舌簧继电器亮相汽车测试博览会
2024-08-26

100
采用MCU+MPU双处理器架构实现的创新应用设计探索
2024-08-23

114

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62126EV30_11

CY62126EV30_11 数据手册

与CY62126EV30_11相关器件

与CY62126EV30_11相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62126EV30_11

CY62126EV30_11 数据手册

与CY62126EV30_11相关器件

与CY62126EV30_11相关文章

您还可以找

您在本页遇到什么问题？