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CY62127BVLL-55ZIT PDF预览

CY62127BVLL-55ZIT

更新时间： 2024-09-15 20:39:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 189K
描述
Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44

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CY62127BVLL-55ZIT 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.76
最长访问时间：55 nsJESD-30 代码：R-PDSO-G44
长度：18.415 mm内存密度：1048576 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：44
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.194 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

CY62127BVLL-55ZIT 数据手册

 浏览型号CY62127BVLL-55ZIT的Datasheet PDF文件第2页浏览型号CY62127BVLL-55ZIT的Datasheet PDF文件第3页浏览型号CY62127BVLL-55ZIT的Datasheet PDF文件第4页浏览型号CY62127BVLL-55ZIT的Datasheet PDF文件第5页浏览型号CY62127BVLL-55ZIT的Datasheet PDF文件第6页浏览型号CY62127BVLL-55ZIT的Datasheet PDF文件第7页 
CY62127BV  
64K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
Features  
• 2.7V–3.6V operation  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
1
8
written into the location specified on the address pins (A  
• CMOS for optimum speed/power  
• Low active power (70 ns, LL version)  
— 54 mW (max.) (15 mA)  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
15  
from I/O pins (I/O through I/O ) is written into the location  
9
16  
specified on the address pins (A through A ).  
0
15  
• Low standby power (70 ns, LL version)  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
— 54 W (max.) (15 A)  
µ
µ
• Automatic power-down when deselected  
Power down either with CE or BHE and BLE HIGH  
—
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
1
8
• Independent control of Upper and Lower Bytes  
• Available in 44-pin TSOP II (forward) and fBGA  
LOW, then data from memory will appear on I/O to I/O . See  
9
16  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
Functional Description  
The input/output pins (I/O through I/O ) are placed in a  
1
16  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY62127BV is a high-performance CMOS Static RAM  
organized as 65,536 words by 16 bits. This device has an au-  
tomatic power-down feature that significantly reduces power  
consumption by 99% when deselected. The device enters  
power-down mode when CE is HIGH or when CE is LOW and  
both BLE and BHE are HIGH.  
The CY62127BV is available in standard 44-pin TSOP Type II  
(forward pinout) and fBGA packages.  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A12  
A11  
A10  
A9  
A
A
2
7
OE  
A
1
BHE  
BLE  
I/O  
A
0
CE  
A7  
A6  
A3  
A2  
A1  
64K x 16  
I/O  
7
1
16  
I/O1–I/O8  
37  
36  
35  
34  
33  
RAM Array  
1024 X 1024  
I/O  
I/O  
8
I/O  
I/O  
2
3
15  
14  
13  
9
I/O9–I/O16  
10  
11  
12  
13  
I/O  
V
I/O  
4
V
SS  
CC  
V
V
SS  
CC  
A0  
I/O  
32  
I/O  
I/O  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
19  
A
A
14  
13  
9
10  
11  
A
20  
21  
22  
A
A
BHE  
A
12  
WE  
CE  
OE  
24  
23  
NC  
NC  
BLE  
62127BV–1  
62127BV–2  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
June 14, 2000  
1234567...10

中文翻译

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CY62127BVLL-55ZIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62127DV30LL-55ZIT CYPRESS

功能相似

 Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62126BVLL-55ZIT CYPRESS

功能相似

 Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62126DV30LL-55ZXIT CYPRESS

功能相似

 Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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