Datasheet > CY62127DV18

CY62127DV18

更新时间： 2024-11-04 21:53:19

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	217K
描述
1M (64K x 16) Static RAM

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CY62127DV18 数据手册

CY62127DV18

MoBL2^®

ADVANCE

INFORMATION

1M (64K x 16) Static RAM

BLE are HIGH. The input/output pins (I/O₀through I/O₁₅) are

placed in a high-impedance state when: deselected Chip En-

able 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW, outputs are

disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH) or during a write oper-

ation (Chip Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂)

HIGH and WE LOW).

Features

• Very high speed: 55 ns

• Voltage range: 1.65V to 1.95V

• Ultra-low active power

— Typical active current: 0.5 mA @ f = 1 MHz

— Typical active current: 2.5 mA @ f = f_MAX

• Ultra-low standby power

• EasymemoryexpansionwithCE₁, CE₂andOE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) LOW and Chip Enable 2 (CE₂) HIGH and Write Enable

(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇), is written into the location

specified on the address pins (A₀through A₁₅). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₅).

• Packages offered in a 48-ball FBGA and a 44-pin TSOP

Type II

Functional Description^[1]

Reading from the device is accomplished by taking Chip En-

able 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH.

If Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins will appear on I/O₀to

I/O₇. If Byte High Enable (BHE) is LOW, then data from mem-

ory will appear on I/O₈to I/O₁₅. See the truth table at the back

of this data sheet for a complete description of read and write

modes.

The CY62127DV18 is a high-performance CMOS static RAM

organized as 64K words by 16 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life (MoBL^®) in portable

applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces

power consumption by 99% when addresses are not toggling.

The device can be put into standby mode reducing power con-

sumption by more than 99% when deselected Chip Enable 1

(CE₁) HIGH or Chip Enable 2 (CE₂) LOW or both BHE and

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A ₉

A ₈

A ₇

A ₆

A ₅

A ₄

A ₃

A ₂

64K × 16

RAM ARRAY

2048 x 32 x 16

I/O₀–I/O₇

I/O₈–I/O₁₅

A ₁

A ₀

COLUMN DECODER

BHE

BLE

Po we r-d o wn

Circ uit

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05226 Rev. **

Revised September 24, 2002

12 3 4 5 6 7...13

中文翻译

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