CY62127DV30L-70ZSI

更新时间： 2024-01-12 01:09:54

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	375K
描述
1 Mb (64K x 16) Static RAM

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技术参数
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CY62127DV30L-70ZSI 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	TSOP2
包装说明：	TSOP2,	针数：	44
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.83
最长访问时间：	70 ns	JESD-30 代码：	R-PDSO-G44
JESD-609代码：	e0	长度：	18.415 mm
内存密度：	1048576 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	16	湿度敏感等级：	3
功能数量：	1	端子数量：	44
字数：	65536 words	字数代码：	64000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	64KX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	座面最大高度：	1.194 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.2 V
标称供电电压 (Vsup)：	3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	10.16 mm
Base Number Matches：	1

CY62127DV30L-70ZSI 数据手册

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CY62127DV30

MoBL^®

1 Mb (64K x 16) Static RAM

also has an automatic power-down feature that significantly

reduces power consumption by 90% when addresses are not

toggling. The device can be put into standby mode reducing

power consumption by more than 99% when deselected (CE

HIGH or both BHE and BLE are HIGH). The input/output pins

(I/O₀through I/O₁₅) are placed in a high-impedance state

when: deselected (CE HIGH), outputs are disabled (OE

HIGH), both Byte High Enable and Byte Low Enable are

disabled (BHE, BLE HIGH) or during a write operation (CE

LOW and WE LOW).

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₅). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₅).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

Features

• Very high speed: 45 ns

• Wide voltage range: 2.2V to 3.6V

• Pin compatible with CY62127BV

• Ultra-low active power

— Typical active current: 0.85 mA @ f = 1 MHz

— Typical active current: 5 mA @ f = f_MAX

• Ultra-low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• Packages offered in a 48-ball FBGA and a 44-lead TSOP

Type II

• Also available in Lead-Free 48-ball FBGA, and 44-lead

TSOP Type II packages

Functional Description^[1]

The CY62127DV30 is a high-performance CMOS static RAM

organized as 64K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

64K x 16

RAM Array

2048 x 512

I/O₀– I/O₇

I/O₈– I/O₁₅

COLUMN DECODER

BHE

BLE

Power -Down

Circuit

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05229 Rev. *D

Revised February 2, 2005

12 3 4 5 6 7...12

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