Datasheet > CY62127DV18_05

CY62127DV18_05

更新时间： 2024-11-05 04:53:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	223K
描述
1 Mb (64K x 16) Static RAM

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CY62127DV18_05 数据手册

CY62127DV18

MoBL2

PRELIMINARY

1 Mb (64K x 16) Static RAM

power consumption by 99% when addresses are not toggling.

The device can be put into standby mode reducing power con-

sumption by more than 99% when deselected Chip Enable

(CE) HIGH or both BHE and BLE are HIGH. The input/output

pins (I/O₀through I/O₁₅) are placed in a high-impedance state

when: deselected Chip Enable (CE) HIGH, outputs are dis-

abled (OE HIGH), both Byte High Enable and Byte Low Enable

are disabled (BHE, BLE HIGH) or during a write operation

(Chip Enable (CE) LOW and Write Enable (WE) LOW).

Features

• Very high speed: 55 ns

• Voltage range: 1.65V to 2.2V

• Ultra-low active power

— Typical active current: 0.5 mA @ f = 1 MHz

— Typical active current: 3.75 mA @ f = f_MAX

• Ultra-low standby power

• Easy memory expansion with CE</> and OE</> fea-

tures

• Automatic power-down when deselected

• Packages offered in a 48-ball FBGA and a 44-lead TSOP

Type II

Writing to the device is accomplished by taking Chip Enable

(CE) LOW and Write Enable (WE) input LOW. If Byte Low

Enable (BLE) is LOW, then data from I/O pins (I/O₀through

I/Os pins (A₀through A₁₅). If Byte High Enable (BHE) is LOW,

then data from I/O pins (I/O₈through I/O₁₅) is written into the

location specified on the ad

Functional Description^[1]

Reading from the device is accomplished by taking Chip En-

able (CE) LOW and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then O₇. If Byte High Enable (BHE) is LOW, then data from

memory will appear on I/O₈to I/O₁₅. See the truth table at the

back of this data sheet for a complete description of re

The CY62127DV18 is a high-performance CMOS static RAM

organized as 64K words by 16 bits. This device features ad-

vanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has

an automatic power-down feature that significantly reduces

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

A₂

A₁

A₀

64K x 16

RAM Array

2048 X 512

I/O₀–I/O₇

I/O₈–I/O₁₅

COLUMN DECODER

BHE

BLE

Power -Down

Circuit

BHE

BLE

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05226 Rev. *A

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised May 5, 2005

12 3 4 5 6 7...11

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与CY62127DV18_05相关器件

型号	品牌	获取价格	描述	数据表
CY62127DV18L-55BVI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV18L-55ZI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV18LL-55BVI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV18LL-55ZI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV20	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV20L-55BVI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV20L-55ZI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV20LL-55BVI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV20LL-55ZI	CYPRESS	获取价格	1M (64K x 16) Static RAM
CY62127DV30	CYPRESS	获取价格	1 Mb (64K x 16) Static RAM

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