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CY62126DV30LL-55ZXIT PDF预览

CY62126DV30LL-55ZXIT

更新时间： 2024-01-28 02:51:53
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
13页 247K
描述
Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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CY62126DV30LL-55ZXIT 技术参数

生命周期：Obsolete零件包装代码：TSOP2
包装说明：TSOP2,针数：44
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.59
最长访问时间：55 nsJESD-30 代码：R-PDSO-G44
JESD-609代码：e3/e4长度：18.415 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：44字数：65536 words
字数代码：64000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX16封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：1.194 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN/NICKEL PALLADIUM GOLD端子形式：GULL WING
端子节距：0.8 mm端子位置：DUAL
宽度：10.16 mmBase Number Matches：1

CY62126DV30LL-55ZXIT 数据手册

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CY62126DV30  
MoBL®  
1-Mbit (64K x 16) Static RAM  
This is ideal for providing More Battery Life™ (MoBL®) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 90% when addresses are not  
toggling. The device can be put into standby mode reducing  
power consumption by more than 99% when deselected (CE  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE HIGH),  
outputs are disabled (OE HIGH), both Byte High Enable and  
Byte Low Enable are disabled (BHE, BLE HIGH) or during a  
write operation (CE LOW and WE LOW).  
Features  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Very high speed: 45 ns  
• Wide voltage range: 2.2V to 3.6V  
• Pin compatible with CY62126BV  
• Ultra-low active power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A15).  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMAX  
• Ultra-low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• Packages offered in a 48-ball FBGA, 56-lead QFN and  
a 44-lead TSOP Type II  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Also available in Lead-free packages  
Functional Description[1]  
The CY62126DV30 is a high-performance CMOS static RAM  
organized as 64K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
64K x 16  
RAM Array  
2048 x 512  
I/O0–I/O7  
I/O8–I/O15  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05230 Rev. *G  
• 3901 North First Street  
• San Jose, CA 95134  
• 408-943-2600  
Revised May 30, 2005  
1234567...13

中文翻译

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CY62126DV30LL-55ZXIT 替代型号

型号 品牌 替代类型 描述 数据表
IS62WV6416BLL-55TLI ISSI

功能相似

 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
CY62126DV30L-55ZSXE CYPRESS

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 1-Mbit (64K x 16) Static RAM

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CY62126DV30LL-70BVI ROCHESTER

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 		64KX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, VFBGA-48
CY62126DV30LL-70BVXI CYPRESS

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 		Standard SRAM, 64KX16, 70ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62126DV30LL-70BVXI ROCHESTER

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 		Standard SRAM, 64KX16, 70ns, CMOS, 8 X 8 MM, LEAD FREE, QFN-56
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 		64KX16 STANDARD SRAM, 70ns, PDSO44, TSOP2-44
CY62126DV30LL-70ZSI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY62126DV30LL-70ZSXI CYPRESS

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 		1-Mbit (64K x 16) Static RAM
CY62126DV30LL-70ZXI CYPRESS

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 		暂无描述

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