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CY62126ESL-45ZSXI PDF预览

CY62126ESL-45ZSXI

更新时间: 2024-09-13 09:42:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 408K
描述
1-Mbit (64K x 16) Static RAM

CY62126ESL-45ZSXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSOP2, TSOP44,.46,32
针数:44Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:5.7
最长访问时间:45 ns其他特性:IT CAN ALSO OPERATES WITH 4.5V TO 5.5V SUPPLY
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e4长度:18.415 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3/5 V认证状态:Not Qualified
座面最大高度:1.194 mm最大待机电流:0.000003 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.016 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:10.16 mmBase Number Matches:1

CY62126ESL-45ZSXI 数据手册

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CY62126ESL MoBL®  
1-Mbit (64K x 16) Static RAM  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99 percent when deselected (CE HIGH). The input and  
output pins (IO0 through IO15) are placed in a high impedance  
state when the device is deselected (CE HIGH), the outputs are  
disabled (OE HIGH), both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH) or during a write  
operation (CE LOW and WE LOW).  
Features  
Very high speed: 45 ns  
Wide voltage range: 2.2V–3.6V and 4.5V–5.5V  
Ultra low standby power  
Typical standby current: 1 μA  
Maximum standby current: 4 μA  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from IO pins (IO0 through IO7) is written into the location  
specified on the address pins (A0 through A15). If Byte High  
Ultra low active power  
Typical active current: 1.3 mA at f = 1 MHz  
Easy memory expansion with CE, and OE features  
Automatic power down when deselected  
CMOS for optimum speed and power  
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15  
)
is written into the location specified on the address pins (A0  
through A15).  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on IO0 to IO7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on IO8 to IO15. See the Truth Table on page 10 for a  
complete description of read and write modes.  
Available in Pb-free 44-Pin TSOP II package  
Functional Description  
The CY62126ESL is a high performance CMOS static RAM  
organized as 64K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
64K x 16  
IO0–IO7  
RAM Array  
IO8–IO15  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 001-45076 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised June 15, 2009  
[+] Feedback  

CY62126ESL-45ZSXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62126ESL-45ZSXA CYPRESS

完全替代

Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126ESL-45ZSXIT CYPRESS

完全替代

Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSSOP2-44
CY62126ESL-45ZSXAT CYPRESS

完全替代

Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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